103,417 research outputs found
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints
No full textSupply voltage scaling and adaptive body-biasing are important tech-niques that help to reduce the energy dissipation of embedded systems. This is achieved by dynamically adjusting the voltage and performance settings according to the application needs. In order to take full ad-vantage of slack that arises from variations in the execution time, it is important to recalculate the voltage (performance) settings during run-time, i.e., online. However, voltage scaling (VS) is computationally ex-pensive, and thus significantly hampers the possible energy savings. To overcome the online complexity, we propose a quasi-static voltage scal-ing scheme, with a constant online time complexity O(1). This allows to increase the exploitable slack as well as to avoid the energy dissipated due to online recalculation of the voltage settings. We conduct several experiments that demonstrate the advantages of the proposed technique over the previously published voltage scaling approaches
Synthesising Energy-Efficient Embedded Systems with LOPOCOS
No full textIn this paper, we introduce the LOPOCOS (Low Power Co-synthesis) system, a prototype CAD tool for system level co-design. LOPOCOS targets the design of energy-efficient embedded systems, implemented as heterogeneous distributed architectures. In particular, it is designed to solve the specific problems involved in architectures that include dynamic voltage scalable (DVS) processors. The aim of this paper is to demonstrate how LOPOCOS can support the system designer in identifying energy-efficient hardware/software implementations for the desired embedded systems. Hence, highlighting the necessary optimisation steps during design space exploration for DVS enable architectures. The optimisation steps carried out in LOPOCOS involve component allocation and task/communication mapping as well as scheduling and dynamic voltage scaling. LOPOCOS has the following key features, which contribute to this energy efficiency. During the voltage scaling valuable power profile information of task execution is taken into account, hence, the accuracy of the energy estimation is improved. A combined optimisation for scheduling and communication mapping based on genetic algorithm, optimises simultaneously execution order and communication mapping towards the utilisation of the DVS processors and timing behaviour. Furthermore, a separation of task and communication mapping allows a more effective implementation of both task and communication mapping optimisation steps. Extensive experiments are conducted to demonstrate the efficiency of LOPOCOS. We report up to 38% higher energy reductions compared to previous co-synthesis techniques for DVS systems. The investigations include a real-life example of an optical flow detection algorithm
Synthesizing Energy-Efficient Embedded Systems with LOPOCOS
No full textIn this paper, we introduce the LOPOCOS (Low Power Co-synthesis) system, a prototype CAD tool for system level co-design. LOPOCOS targets the design of energy-efficient embedded systems, implemented as heterogeneous distributed architectures. In particular, it is designed to solve the specific problems involved in architectures that include dynamic voltage scalable (DVS) processors. The aim of this paper is to demonstrate how LOPOCOS can support the system designer in identifying energy-efficient hardware/software implementations for the desired embedded systems. Hence, highlighting the necessary optimisation steps during design space exploration for DVS enable architectures. The optimisation steps carried out in LOPOCOS involve component allocation and task/communication mapping as well as scheduling and dynamic voltage scaling. LOPOCOS has the following key features, which contribute to this energy efficiency. During the voltage scaling valuable power profile information of task execution is taken into account, hence, the accuracy of the energy estimation is improved. A combined optimisation for scheduling and communication mapping based on genetic algorithm, optimises simultaneously execution order and communication mapping towards the utilisation of the DVS processors and timing behaviour. Furthermore, a separation of task and communication mapping allows a more effective implementation of both task and communication mapping optimisation steps. Extensive experiments are conducted to demonstrate the efficiency of LOPOCOS. We report up to 38% higher energy reductions compared to previous co-synthesis techniques for DVS systems. The investigations include a real-life example of an optical flow detection algorithm
Expression of Alpha-1-Antitrypsin in T-cell lymphocytes
No full textI have studied immunoblastic T-cell lymphoma and enteropathy associated T-cell lymphoma using immunohistochemical techniques for the demonstration of AlAT. Cytoplasmic staining for AlAT is present in the malignant cells of both types of T-cell neoplasm which also express CD30 and CD25. Peripheral blood T-lymphocytes on stimulation with mitogen also show granular cytoplasmic expression of AlAT. Time course studies show that this parallels the expression of CD30 and CD25, markers of lymphoid activation. AlAT expression appears therefore to be associated with activation in T-cells. Further studies of subfractionated T-lymphocytes suggest that the expression of AlAT on activation is not restricted to an individual lymphocyte subset. This study demonstrates AlAT mRNA in monocytes, granulocytes and lumphocytes stimulated with con-A, using synthetic oligonucleotide gene probes. Our results confirm AlAT synthesis by these cells. These cells also express exons A and B, exons not expressed in the hepatocyte. Using probes for the individual exons we have demonstrated alternative splicing of exon B in monocytes and lymphocytes.</p
Co-Synthesis of Energy-Efficient Multi-Mode Embedded Systems with Consideration of Mode Execution Probabilities
No full textWe present a novel co-design methodology for the synthesis of energy-efficient embedded systems. In particular, we concentrate on distributed embedded systems that accommodate several different applications within a single device, i.e., multimode embedded systems. Based on the key observation that operational modes are executed with different probabilities, that is, the system spends uneven amounts of time in the different modes, we develop a new co-design technique that exploits this property to significantly reduce energy dissipation. Energy and cost savings are achieved through a suitable synthesis process that yields better hardware-resource-sharing opportunities. We conduct several experiments, including a realistic smart phone example, that demonstrate the effectiveness of our approach. Reductions in power consumption of up to 64% are reported
Considering Power Variations of DVS Processing Elements for Energy Minimisation in Distributed Systems
No full textDynamic voltage scaling (DVS) is a powerful technique to reduce power dissipation in embedded systems. Some efficient DVS algorithms have been recently proposed for the energy reduction in distributed system. However, they achieve the energy savings solely by scaling the system task with respect to the timing constraints, while neglecting that power varies among the tasks executed by DVS processing elements (DVS-PEs). In this paper we investigate the problem of considering DVS-PE power variations dependent on the executed tasks, during the synthesis of distributed embedded systems and its impact on the energy savings. Unlike previous approaches, which minimise the energy consumption by exploiting the available slack time without considering the PE power profiles, a new and fast heuristic for the voltage scaling problem is proposed, which improves the voltage selection for each task dependent on the individual power dissipation caused by that task. Experimental results show that energy reductions with up to 80.7% are achieved by integrating the proposed DVS algorithm, which considers the PE power profiles, into the co-synthesis of distributed systems
Low Power Process Assignment for Distributed Embedded Systems using Dynamic Voltage Scaling
No full textThis paper presents an efficient algorithm for voltage scaling of an distributed embedded system taking communicating processes into account. The algorithm finds scaled voltages for each processes without restricting the applicable voltage levels apriori. In addition the algorithm is not limited by a fixed power consumption among processes. Furthermore we show the importance of a process optimisation which is optimised for the dynamic voltage scaling (DVS) technique. Various examples from the literature and randomly generate show the efficiency of the proposed scaling algorithm and the DVS optimised process assignment
Application of Analog Adaptive Filters for Dynamic Sensor Compensation
No full textThis paper investigates the application of analog adaptive techniques to the area of dynamic sensor compensation, of which there is little reported work in the literature. The case is illustrated by showing how the response of a load cell can be improved to speed up the process of measurement. The load cell is a sensor with an oscillatory output in which the measurand contributes to the response parameters. Thus, a compensation filter needs to track variation in measurand whereas a simple, fixed filter is only valid at one specific load value. To facilitate this investigation, computer models for the load cell and the adaptive compensation filter have been developed. To allow a practical implementation of the adaptive techniques, a novel piecewise linearization technique is proposed in order to vary a floating voltage-controlled resistor in a linear manner over a wide range. Simulation and practical results are presented, thus demonstrating the effectiveness of the proposed techniques
Modified Isolation Rings for Parallel Test Access in Core Based SoC
No full textOne of the major issues in implementing core-based systems on a chip (SoC) is testing of cores. This paper presents a method to add parallel test access to cores within the SoC for speeding up the system testing time. This involves the introduction of multiple insertion and extraction points in the existing isolation ring of the core and performing the functions of shifting and bypassing simultaneously. To compute the gain in overall testing time ring parameters are introduced and an example demonstrating the efficiency of the proposed method is given
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