140 research outputs found
Automatic content adaptation applied in an interactive environment with individualized learning.
No full textSistemas tutores inteligentes têm se destacado como ferramenta de apoio ao ensino, principalmente pela sua adaptação às condições do usuário e cenário de aplicação. Esta adaptabilidade é possível pela utilização de inteligência artificial. Além disso, a tarefa de ensino é melhor conduzida aplicando-se técnicas como aprendizagem de máquina, processamento de linguagem natural e mineração de dados para adequar o sistema a partir de informações coletadas do usuário em sua utilização.
Apesar disso, essas técnicas ainda não são fortemente exploradas para geração de conteúdo em sistemas tutores. A maioria das aplicações envolve o controle das informações e a orientação dos estudos de seus usuários por meio de recomendação de conteúdo existente. A produção de conteúdo personalizado surge, nesse cenário, como alternativa ao processo de simples recomendação, permitindo que conteúdos apresentem diferentes formatos segundo a personalidade de cada usuário.
Este trabalho desenvolveu uma metodologia de adaptação de conteúdo para ensino, aplicando técnicas de processamento de texto. O processo de produção de conteúdo personalizado permitiu um avanço na forma de uso de sistemas tutores no ensino quanto a geração de conteúdo. Como resultado foi obtido um modelo, com ferramenta aplicada ao contexto, para adaptação automática de conteúdo construído com base em estilos de aprendizagem.Intelligent tutoring systems have stood out as a teaching support tool, mainly due to their ability to adapt to user conditions and application scenarios. This adaptability is possible through the use of artificial intelligence. Furthermore, the creation and adaptation of materials for the system is best conducted by applying techniques such as machine learning, natural language processing and data mining. Despite this, these techniques are not yet heavily explored for generating content in tutoring systems. Most applications involve controlling information and guiding their users' studies by recommending existing content. The production of personalized content appears, in this scenario, as an alternative to the simple recommendation process, allowing content to present different formats according to the personality of each user.
This work developed a methodology for adapting teaching content, applying natural language processing techniques. The process of producing personalized content allowed an advance in the way tutoring systems are used in teaching regarding content generation. As a result, a model was obtained, with a tool applied to the context, for automatic adaptation of content based on learning styles
Performance implications of dynamic memory allocators on transactional memory systems
No full textFundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)Although dynamic memory management accounts for a significant part of the execution time on many modern software systems, its impact on the performance of transactional memory systems has been mostly overlooked. In order to shed some light into this subject, this paper conducts a thorough investigation of the interplay between memory allocators and software transactional memory (STM) systems. We show that allocators can interfere with the way memory addresses are mapped to versioned locks on state-of-the-art software transactional memory implementations. Moreover, we observed that key aspects of allocators such as false sharing avoidance, scalability, and locality have a drastic impact on the final performance. For instance, we have detected performance differences of up to 171% in the STAMP applications when using distinct allocators. Moreover, we show that optimizations at the STM-level (such as caching transactional objects) are not effective when a modern allocator is already in use. All in all, our study highlights the importance of reporting the allocator utilized in the performance evaluation of transactional memory systems.Although dynamic memory management accounts for a significant part of the execution time on many modern software systems, its impact on the performance of transactional memory systems has been mostly overlooked. In order to shed some light into this subje5088796FAPESP - FUNDAÇÃO DE AMPARO À PESQUISA DO ESTADO DE SÃO PAULOFundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)FAPESP [2011/19373-6]2011/19373-
LUTS: A lightweight user-level transaction scheduler
No full textSoftware Transactional Memory (STM) systems have poor performance under high contention scenarios. Since many transactions compete for the same data, most of them are aborted, wasting processor runtime. Contention management policies are typically used to avoid that, but they are passive approaches as they wait for an abort to happen so they can take action. More proactive approaches have emerged, trying to predict when a transaction is likely to abort so its execution can be delayed. Such techniques are limited, as they do not replace the doomed transaction by another or, when they do, they rely on the operating system for that, having little or no control on which transaction should run. In this paper we propose LUTS, a Lightweight User-Level Transaction Scheduler, which is based on an execution context record mechanism. Unlike other techniques, LUTS provides the means for selecting another transaction to run in parallel, thus improving system throughput. Moreover, it avoids most of the issues caused by pseudo parallelism, as it only launches as many system-level threads as the number of available processor cores. We discuss LUTS design and present three conflict-avoidance heuristics built around LUTS scheduling capabilities. Experimental results, conducted with STMBench7 and STAMP benchmark suites, show LUTS efficiency when running high contention applications and how conflict-avoidance heuristics can improve STM performance even more. In fact, our transaction scheduling techniques are capable of improving program performance even in overloaded scenarios. © 2011 Springer-Verlag.IC-UNICAMPUNESP - Univ. Estadual Paulista, Rio ClaroUNESP - Univ. Estadual Paulista, Rio Clar
Energy-aware scheduling in transactional memory systems
No full textTransaction scheduling is a relatively new technique for transactional memory systems responsible for deciding which transactions to run in a given moment. Current transactional schedulers are designed with performance in mind, leaving unattended other important metrics such as energy consumption. In order to address this important concern, this paper presents a novel heuristic, called Dynamic Serializer (DS), for scheduling transactions with the aim of reducing energy consumption and improving the energy-delay product (EDP) of transactional applications. DS serializes the execution by choosing either a spinlock or mutex according to a dynamic profile based on abort rates. The idea is to use a spinlock when a transaction is likely to succeed in the near future, since spinning while waiting for the lock is faster than blocking as in the case of a mutex. On the other hand, a mutex is used in case transactions need to wait a long time before resuming because in this case energy can be saved by blocking a thread and enabling the processor Dynamic Voltage and Frequency Scaling (DVFS) to act. DS exploits this tradeoff to improve the EDP of transactional programs. Experimental results with an Intel Core i7 with 8 logical threads and the STAMP benchmark show an EDP improvement of up to 17% and an average of 4.9% compared to LUTS-Dynamic, a state-of-the-art scheduling heuristic for transactional systems.Fundação de Amparo à Pesquisa do Estado de São Paulo (FAPESP)Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)UNESP Univ Estadual PaulistaUNESP Univ Estadual PaulistaFAPESP: 2011/19373-6CNPq: 446160/2014-
FGSCM: A Fine-Grained Approach to Transactional Lock Elision
No full textSpeculative Lock Elision (SLE) is a technique that allows critical sections to be executed optimistically by eliding the lock operation and enabling multiple threads to execute concurrently. In case of inconsistencies, the hardware automatically rolls back the execution and pessimistically acquires the original lock during runtime. The decision to elide the lock in SLE is performed transparently at the microarchitecture level and, although being convenient, it may sometimes hurt performance. To avoid that case, researchers have investigated Transactional Lock Elision (TLE), in which software-controlled hardware transactions are used instead, allowing the creation of policies and heuristics to manage lock elision. Typical implementations of TLE make use of a single lock to serialize the execution in case the original lock cannot be elided, which can potentially degrade performance. In order to improve on such cases, this paper proposes the Fine-Grained Software-assisted Conflict Management (FGSCM) scheme, a TLE technique that employs multiple locks so as to avoid unnecessary serialization of the code. The main idea of FGSCM is that not all threads that conflict inside a critical section are acessing the same region of shared memory. By automatically assigning distinct locks to these threads according to the memory section they access, the level of concurrency can be increased. In this paper we formalize FGSCM and provide an in-depth performance evaluation using a microbenchmark to stress several conflict behaviors. Our initial results with a prototype implementation using Intels Restricted Transactional Memory (RTM) are encouraging. With a quadcore machine, we observed an average performance gain of 11% compared to the single-auxiliary-lock SCM and 36% compared to a standard lock scheme, both for typical read-dominated workloads.Conselho Nacional de Desenvolvimento Científico e Tecnológico (CNPq)Univ Estadual Paulista - UNESPUniv Estadual Paulista - UNESPCNPq: 446160/2014-
Improving Speculative taskloop in Hardware Transactional Memory
No full textPrevious work proposed and evaluated Speculative taskloop (STL) on Intel Core implementing new clauses and constructs in OpenMP. The results indicated that, despite achieving some speed-ups, there was a phenomenon called the Lost-Thread Effect that caused the performance degradation of STL parallelization. This issue is caused by the nonmonotonic scheduling implemented in the LLVM OpenMP Runtime Library. This paper presents an improvement in the STL mechanism by modifying the OpenMP runtime to allow monotonic scheduling of tasks generated by taskloop. We perform an evaluation with two different versions of the OpenMP runtime, both optimized for STL revealing that, for certain loops, infinite slowdowns (deadlocks) using the original OpenMP runtime can be transformed in speed-ups by applying monotonic scheduling. The experimental results show the performance improvement of STL using the modified version of the runtime, reaching speed-ups of up to 2.18 ×.IGCE – Sao Paulo State University (Unesp)IGCE – Sao Paulo State University (Unesp
Using Hardware Transactional Memory to Implement Speculative Privatization in OpenMP
No full textLoop Thread-Level Speculation on Hardware Transactional Memories is a promising strategy to improve application performance in the multicore era. However, the reuse of shared scalar or array variables introduces constraints (false dependences or false sharing) that obstruct efficient speculative parallelization. Speculative privatization relieves these constraints by creating speculatively private data copies for each transaction thus enabling scalable parallelization. To support it, this paper proposes two new OpenMP clauses to parallel for that enable speculative privatization of scalar or arrays in may DOACROSS loops: spec_private and spec_reduction. We also present an evaluation that reveals that, for certain loops, speed-ups of up to 3.24 × can be obtained by applying speculative privatization in TLS.São Paulo State University, SPSão Paulo State University, S
Exploiting software transactional memory in the context of asymmetric architectures
Get PDFOrientador: Paulo Cesar CentoducatteTese (doutorado) - Universidade Estadual de Campinas, Instituto de ComputaçãoResumo: A adoção dos microprocessadores com múltiplos núcleos de execução pela indústria semicondutora tem criado uma crescente necessidade por novas linguagens, metodologias e ferramentas que tornem o desenvolvimento de sistemas concorrentes mais rápido, eficiente e acessível aos programadores de todos os níveis. Uma das principais dificuldades em programação concorrente com memória compartilhada é garantir a correta sincronização do código, evitando assim condições de corrida que podem levar o sistema a um estado inconsistente. A sincronização tem sido tradicionalmente realizada através de métodos baseados em travas, reconhecidos amplamente por serem de difícil uso e pelas anomalias causadas. Um novo mecanismo, conhecido como memória transacional (TM), tem sido alvo de muita pesquisa recentemente e promete simplificar o processo de sincronização, além de possibilitar maior oportunidade para extração de paralelismo e consequente desempenho. O cerne desta tese é formado por três trabalhos desenvolvidos no contexto dos sistemas de memória transacional em software (STM). Primeiramente, apresentamos uma implementação de STM para processadores assimétricos, usando a arquitetura Cell/B.E. como foco. Como principal resultado, constatamos que o uso de sistemas transacionais em arquiteturas assimétricas também é promissor, principalmente pelo fator escalabilidade. No segundo trabalho, adotamos uma abordagem diferente e sugerimos um sistema de STM especialmente voltado para o domínio de jogos computacionais. O principal motivo que nos levou nesta direção é o baixo desempenho das implementações atuais de STM. Um estudo de caso conduzido a partir de um jogo complexo mostra a eficácia do sistema proposto. Finalmente, apresentamos pela primeira vez uma caracterização do consumo de energia de um sistema de STM considerado estado da arte. Além da caracterização, também propomos uma técnica para redução do consumo em casos de alta contenção. Resultados obtidos a partir dessa técnica revelam ganhos de até 87% no consumo de energiaAbstract: The shift towards multicore processors taken by the semiconductor industry has initiated an era in which new languages, methodologies and tools are of paramount importance to the development of efficient concurrent systems that can be built in a timely way by all kinds of programmers. One of the main obstacles faced by programmers when dealing with shared memory programming concerns the use of synchronization mechanisms so as to avoid race conditions that could possibly lead the system to an inconsistent state. Synchronization has been traditionally achieved by means of locks (or variations thereof), widely known by their anomalies and hard-to-get-it-right facets. A new mechanism, known as transactional memory (TM), has recently been the focus of a lot of research and shows potential to simplify code synchronization as well as delivering more parallelism and, therefore, better performance. This thesis presents three works focused on different aspects of software transactional memory (STM) systems. Firstly, we show an STM implementation for asymmetric processors, focusing on the architecture of Cell/B.E. As an important result, we find out that memory transactions are indeed promising for asymmetric architectures, specially due to their scalability. Secondly, we take a different approach to STM implementation by devising a system specially targeted at computer games. The decision was guided by poor performance figures usually seen on current STM implementations. We also conduct a case study using a complex game that effectively shows the system's efficiency. Finally, we present the energy consumption characterization of a state-of-the-art STM for the first time. Based on the observed characterization, we also propose a technique aimed at reducing energy consumption in highly contended scenarios. Our results show that the technique is indeed effective in such cases, improving the energy consumption by up to 87%DoutoradoSistemas de ComputaçãoDoutor em Ciência da Computaçã
Transaction scheduling using dynamic conflict avoidance
No full textSoftware transaction memory (STM) systems have been used as an approach to improve performance, by allowing the concurrent execution of atomic blocks. However, under high-contention workloads, STM-based systems can considerably degrade performance, as transaction conflict rate increases. Contention management policies have been used as a way to select which transaction to abort when a conflict occurs. In general, contention managers are not capable of avoiding conflicts, as they can only select which transaction to abort and the moment it should restart. Since contention managers act only after a conflict is detected, it becomes harder to effectively increase transaction throughput. More proactive approaches have emerged, aiming at predicting when a transaction is likely to abort, postponing its execution. Nevertheless, most of the proposed proactive techniques are limited, as they do not replace the doomed transaction by another or, when they do, they rely on the operating system for that, having little or no control on which transaction to run. This article proposes LUTS, a lightweight user-level transaction scheduler. Unlike other techniques, LUTS provides the means for selecting another transaction to run in parallel, thus improving system throughput. We discuss LUTS design and propose a dynamic conflict-avoidance heuristic built around its scheduling capabilities. Experimental results, conducted with the STAMP and STMBench7 benchmark suites, running on TinySTM and SwissTM, show how our conflict-avoidance heuristic can effectively improve STM performance on high contention applications. © 2012 Springer Science+Business Media, LLC.Institute of Computing UNICAMP, Campinas SPUniv Estadual Paulista, Rio-Claro SPUniv Estadual Paulista, Rio-Claro S
Automatic generation of assemblers using ArchC
No full textOrientador: Paulo Cesar CentoducatteDissertação (mestrado) - Universidade Estadual de Campinas, Instituto de ComputaçãoResumo: Projetistas de sistemas dedicados enfrentam atualmente novos desafios em todas as fases do projeto. A difusão da tecnologia conhecida como SoC (System on a Chip) requer novos paradigmas para a especificação, implementação e verificação do projeto. A alta complexidade de tais sistemas e a grande variedade de configurações disponíveis podem tornar a escolha do sistema ideal demorada, prolongando o tempo de projeto e conseqüentemente seu ingresso no mercado. Em especial, no processo de escolha de um certo processador, o projetista necessita de um conjunto básico de ferramentas que lhe permitam analisar questões como desempenho, potência consumida, ou ainda área de silício ocupada. Exemplos de ferramentas importantes nessa fase de avaliação do projeto incluem compiladores, montadores e simuladores de instruções. Nesse contexto, o uso de uma linguagem para descrição de arquitetura (Architecture Description Language, ADL) permite que processadores sejam modelados em níveis altos de abstração, e que um conjunto de ferramentas específicas para o modelo descrito seja gerado automaticamente. ArchC é uma ADL em desenvolvimento no Laboratório de Sistemas de Computação (IC-UNICAMP), e já é capaz de gerar ferramentas de simulação de instruções automaticamente. Desenvolvemos neste trabalho uma ferramenta para geração automática de montadores a partir de modelos descritos em ArchC, denominada acasm 2. O desenvolvimento de acasm nos levou a incorporar novas construções a ArchC para a modelagem da linguagem de montagem e da codificação das instruções. Nossa ferramenta gera um conjunto de arquivos dependentes de arquitetura para o redirecionamento do montador GNU Assembler (gas). Usamos acasm para gerar montadores a partir de modelos, em ArchC, das arquiteturas MIPS-I e SPARC-V8, e comparamos os arquivos objetos obtidos com os gerados pelo montador gas nativo para ambas arquiteturas. Os resultados mostraram que os arquivos gerados pelo nosso montador foram idênticos aos gerados pelo montador nativo para ambas arquiteturasAbstract: Nowadays, embedded systems designers are facing new challenges at all stages of the design process. The growing of the system-on-chip (SoC) technology is creating new paradigms in the specification, implementation and verification phases of a design. The increasing complexity and the myriad of available configurations make it hard to choose the ideal system, therefore lengthening the design time, as well as time to market. Specially, customization of the processor architecture requires a software toolkit in order to estimate factors such as performance, power dissipation and chip area. Examples of these tools may include compilers, assemblers and instruction level simulators. In this context, the use of an architecture description language (ADL) allows one to model processors using different levels of abstraction. Based on the model, a software toolkit can be automatically generated. ArchC is an ADL being developed by the Computer Systems Laboratory (IC-UNICAMP) and can automatically generate instruction level simulators at its current stage. In this work, we have created a tool to automatically generate assemblers from ArchC models, named acasm 3. While developing acasm we have introduced new language constructions to ArchC in order to describe the assembly language syntax and the instruction encoding scheme. Our tool retargets the GNU assembler (gas) to different architectures by generating a set of architecture depedent files based on ArchC models. We used acasm to generate assemblers to the MIPS-I and SPARC-V8 architectures based on our ArchC models. We then compared the object files created by our assemblers with the ones created by the native gas and no difference between each pair of files was noticed, for both architecturesMestradoMestre em Ciência da Computaçã
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