3,162 research outputs found
Amplifier and radiation detector
No full textSi tratta di una soluzione per ridurre la capacità d'ingresso di un circuito elettronico pre-amplificatore di segnale di un rivelatore di radiazione ionizzante.
Tale riduzione è ottenuta sfruttando parte o tutta la capacità parassita d'ingresso del circuito per realizzare la capacità di retroazione del pre-amplificatore di carica.
La conseguente riduzione della capacità consente di ridurre il rumore elettronico del sistema rivelatore più pre-amplificatore
The analog channel for the readout of the outer layers of the SuperB SVT
No full textIn this work, we present the design and the results of the analog channel of the readout circuit for the outer layers of SuperB Silicon Vertex Tracker (SVT). In these layers, the strip detectors have a very high stray capacitance and high series resistance. Therefore, the noise optimization was the first priority design concern. To fulfill the noise level and efficiency requirements, a compromise on the best peaking time has been investigated. The ASIC is composed by a classical processing scheme, composed by a preamplifier, shaping amplifier and TOT for the digitalization of the signals. The chosen shaping function is the third-order semi-Gaussian function implemented with complex poles. An inverter stage is employed in the analog channel in order to operate with signals delivered from both p and n strips. The circuit foresees the possibility to select the peaking time of the shaper (250, 375, 500 and 750 ns). In this way, the noise performances and the signal occupancy can be optimized according to the real background during the experiment. The first prototype has been fabricated in the 130nm IBM technology which is considered intrinsically radiation hard. The first results of the experimental characterization of a produced prototype are here presented
An assessment of the impact of possible CAP reform scenarios on Romanian agriculture
No full textUsing a simplified model, with key-variable the prices of two different possible scenarios of CAP reform after 2013 (moderate and radical), this paper present a comparison between the price effects of implementation of each reform scenario at 2015 horizon on Romanian agriculture. This short analysis shows that, under the presented hypotheses, the net welfare effect, due to the price changes, for the selected products, is positive in both reform scenarios, yet greater in the case of the radical reform. Integrated in the large context of Romanian development, it seems that the influence of CAP reform upon agriculture and rural areas will be most likely a gradual one: an interpenetration between the two scenarios is foreseeable, starting with the moderate reform that will dominate the period around 2013, the reform measures acquiring a more radical character afterwards.CAP reform, Romania, welfare effects, Agricultural and Food Policy,
Fast DEPFET current readout for X-ray astronomy missions
No full textThe DEPFET-based Active Pixel Sensor (APS) matrix is a new detector concept for X-ray imaging and spectroscopy applications. This type of detector can provide excellent energy resolution and high-speed readout. Both of these features, along with the advantage of random pixel accessibility, can fulfill the requirements of new imaging applications in the X-ray band. In a matrix arrangement, each pixel must be read Out by a time-variant filter, so a proper multi-channel integrated filtering amplifier is needed. To operate large area matrices at very fast processing times, we have recently proposed a Current readout configuration. in this paper, we explore the performance offered by this circuit when operated with a DEPFET matrix, specifically concerning its ultimate speed capabilities and the trade-off achieved between electronics noise and processing time. (C) 2009 Elsevier B.V. All rights reserved
Rich, Sturmian, and trapezoidal words
No full textIn this paper we explore various interconnections between rich words, Sturmian words, and trapezoidal words. Rich words, first introduced by the second and third authors together with J. Justin and S. Widmer, constitute a new class of finite and infinite words characterized by having the maximal number of palindromic factors. Every finite Sturmian word is rich, but not conversely. Trapezoidal words were first introduced by the first author in studying the behavior of the subword complexity of finite Sturmian words. Unfortunately this property does not characterize finite Sturmian words. In this note we show that the only trapezoidal palindromes are Sturmian. More generally we show that Sturmian palindromes can be characterized either in terms of their subword complexity (the trapezoidal property) or in terms of their palindromic complexity. We also obtain a similar characterization of rich palindromes in terms of a relation between palindromic complexity and subword complexity
"The SIDDHARTA chip: a CMOS multi-channel circuit for Silicon Drift Detectors Readout in Exotic Atoms Research"
No full text
Characterization Results for the Poset Based Representation of Topological Relations - I: Introduction and Models
No full text@article{DBLP:journals/informaticaSI/ForlizziN99,
author = {Luca Forlizzi and
Enrico Nardelli},
title = {Characterization Results for the Poset Based Representation
of Topological Relations - I: Introduction and Models.},
journal = {Informatica (Slovenia)},
volume = {23},
number = {2},
year = {1999},
bibsource = {DBLP, http://dblp.uni-trier.de}
Characterization Results for the Poset Based Representation of Topological Relations - II: Intersection and Union
No full text@article{DBLP:journals/informaticaSI/ForlizziN00,
author = {Luca Forlizzi and
Enrico Nardelli},
title = {Characterization Results for the Poset Based Representation
of Topological Relations - II: Intersection and Union.},
journal = {Informatica (Slovenia)},
volume = {24},
number = {1},
year = {2000},
bibsource = {DBLP, http://dblp.uni-trier.de}
System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing
No full textThis dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications.
Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance.
This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB.
Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy).
The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption.
Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude
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