1,720,956 research outputs found
High Frequency DC-DC Buck Converter for Automotive Post-Regulated Applications
Full text linkThe current trends in the automotive market are pushing toward an ever increasing integration of electronic components in a car. Modern cars need to be safer and smarter, hence there is the need of a lot of sensors, radars, microcontrollers etc. Consequentially, the power supply circuits that are needed to power up all these devices starting from the 12-V battery of a car are also facing an intense thrust to integration. More integration of the power supply circuits means that the production costs and area of the components are significantly reduced, but leads to less flexibility of the circuits and less robustness to high temperatures. The traditional approach was to directly convert the battery voltage to each desired lower voltage using either low dropout regulators(LDOs) or switching DC-DC converters, depending on the application. Nowadays a post-regulated approach is preferred: one converter downshifts the battery voltage to an intermediate one, typically in the range of 4∼8 V, and that intermediate voltage can either directly supply some circuits, or be the input of multiple successive regulators, that will each power up the circuits that require lower supply voltages. While complicating the design, this approach is preferred due to a higher efficiency, and the possibility of a more robust thermal isolation of the circuits. Switching DC-DC converters are usually very expensive and bulky, and this is mostly due to the presence of the inductor, which can often cost more than the chip itself, both in terms of money and area consumption. The typical switching frequency of a DC-DC converter is a few MHz. By increasing the switching frequency, a much lower inductance value can be used without degrading the current ripple. Having a lower value of inductance means that the physical dimension of the inductor is smaller, resulting in an advantage in chip cost and area. In the field of power converters, efficiency is obviously another key parameter, especially in the field of automotive where a high efficiency is beneficial for both environmental and economical reasons. The main topic of this PhD research is the study and of this research is the study and the design of a buck converter with specifications aligned with the post-regulated domain, switching at 50/100 MHz. This work has been possible thanks to the collaboration between the University of Pavia and Infineon Technologies Italy, with help from both the Pavia and Padova sites.
The second topic of this thesis is the design of a Hybrid Single-Inductor Bipolar-Output DC–DC Converter with Floating Negative Output for AMOLED Displays. As AMOLED Displays have become one of the standard technologies for mobile and TV screens, the research for more compact and efficient solutions for the supplies of the pixels is thriving. As AMOLED displays need two supply voltages (one positive and one negative) to turn on, two separate DC-DC converters are typically used to provide the necessary voltages from the battery. A Single-Inductor solution can generate both voltages with only one inductor, hence saving a lot of money and area on the chip. This part of the work has been conducted thanks to the collaboration between the University of Pavia and the University of Macau
Video for On the Design of High Switching Frequency DC-DC Buck Converter Power Stages for Automotive Post-Regulated Applications
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Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Design of a capacitive-coupled integrated circuit for adaptive dead time control and short-circuit fault detection in industrial motor gate drivers
No full textLAUREA MAGISTRALEGli inverter di potenza sono impiegati nei convertitori a frequenza variabile per pilotare motori elettrici industriali e controllarne con precisione la velocità. In questi sistemi, due transistori di potenza ad alta tensione sono configurati in una "gamba di inverter" e commutati alternativamente per generare una tensione a modulazione di larghezza di impulso (PWM) sulla fase del motore, producendo la corrente a bassa frequenza necessaria. A causa delle asimmetrie nella commutazione dei transistor, se i segnali di accensione e spegnimento vengono emessi contemporaneamente, può verificarsi una conduzione simultanea, rischiando di cortocircuitare il bus DC. Per evitare questo fenomeno viene introdotto un ritardo fisso, noto come "dead time", tra la commutazione dei due dispositivi. Durante questo intervallo, la natura induttiva del motore forza la corrente di carico a fluire attraverso i diodi di body dei transistor, causando dissipazione di potenza, perdite di energia e distorsione armonica nella corrente di uscita. Minimizzare il dead time può essere vantaggioso; tuttavia, la sua durata ottimale varia durante il ciclo del motore ed è influenzata dalla polarità della corrente di carico e dal tipo di transizione di commutazione. In questa tesi è stato sviluppato un circuito integrato che determina e applica il dead time ottimale senza la necessità di misurare direttamente la corrente del motore. L’architettura proposta, realizzata con tecnologia BCD fornita da Infineon Technologies, stabilisce il dead time ottimale rilevando la polarità della corrente di carico tramite la misura della velocità di variazione (dV/dt) del nodo di commutazione Vs, utilizzando un condensatore ad alta tensione integrato. L’architettura è stata testata tramite simulazioni, confermando che riduce significativamente il dead time, diminuendo la dissipazione di potenza e la distorsione armonica a bassa frequenza nell’uscita. Infine, è stata implementata e verificata la funzionalità aggiuntiva di rilevamento di cortocircuiti sul carico, ottenuta sfruttando i segnali generati dal blocco per l’ottimizzazione del dead time, con l’aggiunta di una minima circuiteria logica.Power inverters are used in Variable Frequency Drives (VFDs) to drive industrial electric motors and precisely control their speed. In these systems, high-voltage power transistors are configured in inverter legs and alternately switched to produce a Pulse Width Modulated (PWM) voltage on the motor phase, which in turn generates the required lower-frequency current. Due to inherent asymmetries in transistor switching, simultaneous conduction may occur if the turn-on and turn-off signals are issued at the same time, potentially shorting the DC bus and damaging the system. To prevent this, a fixed delay, known as dead time, is introduced between the switching of complementary transistors. However, during this interval, the inductive nature of the motor forces the load current to flow through the transistors’ body diodes, resulting in power dissipation, energy losses, and harmonic distortion in the output current. Minimizing dead time can therefore be beneficial; however, its optimal duration varies throughout the motor cycle, influenced by factors like load current polarity and the type of switching transition. In this thesis, an integrated circuit that determines and applies the optimal dead time without the need for direct motor current sensing has been developed. The proposed architecture, implemented using a BCD technology with deep trenches capability provided by Infineon Technologies, determines the optimal dead time by first determining the load current polarity by means of switching node dV/dt sensing, using an innovative, cost-effective method based on an integrated high-voltage capacitor. The complete architecture has been fully validated through simulations, and its compliance with an existing test chip has been verified. Simulation results confirm that the design minimizes dead time to the lowest possible value, significantly reducing power dissipation and low-frequency harmonic distortion at the output. Finally, the additional feature of load short-circuit detection has been implemented and verified. This functionality is achieved by leveraging the signals produced by the current sensor, with only a minimal addition of logic circuitry
Variations on the Author
Full text link“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Full text linkWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
Dispelling the Myths Behind First-author Citation Counts
Full text linkWe conducted a full-scale evaluative citation analysis study of scholars in the XML research field to explore just how different from each other author rankings resulting from different citation counting methods actually are, and to demonstrate the capability of emerging data and tools on the Web in supporting more realistic citation counting methods. Our results contest some common arguments for the continued
use of first-author citation counts in the evaluation of scholars, such as high correlations between author rankings by first-author citation counts and other citation
counting methods, and high costs of using more realistic citation counting methods that are not well-supported by the ISI databases. It is argued that increasingly available digital full text research papers make it possible for citation analysis studies to go beyond what the ISI databases have directly supported and to employ more
sophisticated methods
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