1,720,975 research outputs found
Time efficiency of CT colonography: 2D vs 3D visualization
No full textWe aimed to compare the time efficiency of three visualization methods in CT colonography and to identify the colonic factors influencing the time for interpretation. Twenty CT colonographic examinations were prospectively analysed. Three reading methods were adopted: method 1, primary 2D analysis with the use of virtual endoscopy as problem solver, method 2, primary standard virtual endoscopy with semiautomatic navigation through the colon and use of 2D images as problem solver; method 3, primary virtual endoscopy with automatic navigation and the use of 2D images as problem solver. In method 1, time for 2D analysis ranged between 6 and 18 min (mean 12) for evaluation of both supine and prone decubitus with a synchronization method. In method 2, time for 3D manual navigation in supine plus prone ranged between 9 and 24 min (mean 17). In method 3, time for automated navigation ranged between 6 and 20 min (mean 12) for evaluation of both supine and prone decubitus. A statistically significant difference was found between time efficiency of methods 1 and 2 (p=0.009, t-test, unequal variances). Methods 2 and 3 showed a tendency to significant differences (p=0.054, t-test, unequal variances). Faecal or fluid residuals were reported as major drawbacks in 3D navigations, requiring constant correlation with 2D images; tortuous folds influenced mostly the 2D analysis; diverticula were reported as influencing factor in all three methods. No differences in sensitivity and specificity were observed between the three viewing methods. The 3D semiautomatic navigation method* tended to increase the time for interpretation in almost all cases. There is, in particular, greatest time efficiency for 2D analysis as compared with 3D manual analysis. Two-dimensional and automated 3D navigation reading have comparable time efficiencies in a routine clinical setting
Energy Behaviour of NUCA caches in CMPs
No full textAbstract—Advances in technology of semiconductor make
nowadays possible to design Chip Multiprocessor Systems equipped with huge on-chip Last Level Caches. Due to the wire delay problem, the use of traditional cache memories with a uniform access time would result in unacceptable response latencies. NUCA (Non Uniform Cache Access) architecture has been proposed as a viable solution to hide the adverse impact of wires delay on performance. Many previous studies have focused on the effectiveness of NUCA architectures, but the study of the energy and power aspects of NUCA caches is still limited.
In this work, we present an energy model specifically suited for NUCA-based CMP systems, together with a methodology to employ the model to evaluate the NUCA energy consumption. Moreover, we present a performance and energy dissipation analysis for two 8-core CMP systems with an S-NUCA and a D-NUCA, respectively. Experimental results show that, similarly to the monolithic processor, the static power also dominates the total power budget in the CMP system
PERFORMANCE OF CT COLONOGRAPHY BASED ON MULTIPLE PRIMARY 3D STEREOSCOPIC DISPLAYS: COLONDEX
No full text
Going Beyond Counting First Authors in Author Co-citation Analysis
Get PDFThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Analysis of Static and Dynamic Energy Consumptions in NUCA Caches: Initial Results
No full textABSTRACT
NUCA caches are large L2 on-chip cache memories characterized by multi-bank partitioning and designed to hide wire delay effects. They exhibit high hit rates while keeping access latency low. Proposed designs for such caches are Static NUCA, in which data are statically allocated to the cache banks, and Dynamic NUCA, in which data may reside in different banks, and a migration mechanism is introduced to better tolerate wire delay
effects. The two architectures permit to achieve different performances by acting on architectural parameters and data management policies, at the cost of different balances between
static and dynamic power consumption and energy dissipation. In this work, we propose preliminary results of the characterization
of such balances, by presenting an evaluation of performance and energy consumption of conventional UCAs, and Static and Dynamic NUCA caches. All the considered caches architectures are equal sized and they are supposed to be used in an aggressive
high frequency system running some applications from the SPEC CPU2000 and the NAS Parallel Benchmarks suites. The experimental results obtained indicate that, although the migration
of data contributes to increase the dynamic energy consumption in Dynamic NUCA caches, the higher IPC achieved permits to save
static energy, which dominates the power/energy balance in all the considered architectures. As a consequence, such results
would designate NUCA caches as the most performing and
energy saving architectures. Besides, according to the obtained results, future power improvements for NUCA caches should concentrate on static energy, while, for the dynamic energy, the on-chip network is the most critical element. Migration of data is
acceptable, since it has a positive impact on performance, and the
increased dynamic energy is overwhelmed by the static energy savings resulting from the shorter execution time. In order to give a general validity to such statements, we need to explore more
design space points for each architecture (by varying the running clock rate and other design parameters) and to evaluate them considering a larger set of benchmark
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