1,720,964 research outputs found
Characterization, Modeling and Design of a 10Gbps Serial Link
No full textThe goal of this PhD has been to model, design and characterize a 10Gbps serial interface suitable for automotive Electronic Control Units (ECU). The work has been carried out in collaboration with Infineon Technology.
High speed serial interfaces are a hot topic both in the academic and industrial world. Due to the stringent safety requirements and the extremely harsh environment in which the link must be able to correctly operate, the automotive sector lags some years behind the consumer market. Thus, the main goal of this work is to bridge the gap between the consumer electronic and the automotive electronic unit world, understanding which techniques are suitable for our working conditions among the ones that are already well established in the academic world and translating and improving these solutions to possibly make them more stable and less power consuming. This goal implies a deep understanding of a serial link both at system and transistor level, and the development of this thesis will follow this idea.
The first part of this work is dedicated to the transmitter: we will start from a system level analysis, creating a methodology to assess the equalization capability that has to be foreseen at transmitter side when dealing when channels typical of the automotive environment. The description of the transistor level design will follow, motivating design choices and supporting them with simulation results and comparison with the state of the art presented in literature. To conclude this first part of the work, measurements of the described transmitter will be presented and discussed.
The second part of the thesis is mainly focused on the receiver. As for the transmitter, we will start with a system level analysis, aimed at understanding the different equalization schemes proposed in the literature. With the help of a Simulink model, an architecture will be proposed. The transistor level analysis of the aforementioned architecture will follow and will be supported by transistor level simulations of the receiver alone and of the complete transceiver, along with the digital control part.
Finally, an experimental characterization of the full link will be presented, analyzing its performances with measurements performed in the design center of Infineon Technologies, Villach (A)
Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications
Full text linkA TCAD-Based Methodology to Model the Site-Binding Charge at ISFET/Electrolyte Interfaces
Full text linkWe propose a new approach to describe in commercial TCAD the chemical reactions that occur at dielectric/electrolyte interface and make the ion sensitive FET (ISFET) sensitive to pH. The accuracy of the proposed method is successfully verified against the available experimental data.
We demonstrate the usefulness of the method by performing, for the first time in a commercial TCAD environment, a full 2-D analysis of ISFET operation, and a comparison between threshold voltage and drain current differential sensitivities in the linear and saturation regimes. The method paves the way to accurate
and efficient ISFET modeling with standard TCAD tools
Modeling of Phase-Interpolator-Based Clock and Data Recovery for High-Speed PAM-4 Serial Interfaces
Full text linkWe have employed a time-domain behavioral simulator to analyze how different design options for bang-bang Clock and Data Recovery (CDR) impact the Jitter Tolerance (JTOL) performance of High-Speed Serial Interfaces (HSSIs) with PAM-4 signaling. The simulator includes the effect of Inter-Symbol Interference (ISI) due to the transmission channel, various equalization schemes and a detailed description of the CDR architecture. Many design options have been investigated, with particular focus on transition filtering and on the algorithm to identify the Early/Late (E/L) information from data and edge samples after deserialization. It has been found that if majority voting is employed to derive a single set of E/L information from an array of phase detectors working on deserialized data and edges, the different filtering strategies provide the same JTOL, meaning that one can avoid transition filtering and furthermore use a single edge sampler with a zero threshold, significantly simplifying the CDR architecture. Instead, if summation of the E/L information from deserialized data and edges is performed, the decision to use one or three thresholds for the edge sampling and the choice of whether to implement transition filtering both impact JTOL; however, better performance is achieved under these conditions than when employing majority voting on the deserialized E/L signals
System and transistor level analysis of an 8-taps FFE 10Gbps serial link transmitter with realistic channels and supply parasitics
No full textCircuit/system level simulations are employed to assess the performance of a 10 Gbps transmitter for a high speed serial interface to be used in automotive Electronic Control Units. The transmitter has been designed in a standard 28 nm technology and features feed-forward equalization (FFE) with 8 taps (1 pre- and 6 post-cursors), whose strength is programmable with 16 discretization steps. It is shown that the parasitic inductance on the supply terminals degrades the performance in
terms of jitter and SNR and tends to hamper the benefits of FFE. When the value of these inductances is minimized, system-level models of the transmitter reproduce quite well time-consuming transistor-level simulations
Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers
No full textThis work describes the design of a transmitter for a
10 Gbps serial interface to be used in automotive Electronic Control
Units. The data rate is chosen in order to assess the design
challenges in automotive environment at this frequency. The focus
will be mainly on challenges related to transistor level design
using a standard 28 nm technology, nevertheless a system level
overview will be also given. The proposed transmitter features
feed-forward equalization with 8 taps (1 pre-cursor and 6 postcursors,
plus the main tap), whose strength is programmable with
16 discretization steps, optimizing the transmitter adaptability
with reduced area. The proposed architecture is also able to
tune its output impedance independently from the choice of the
weights of the equalization tap. It features a 300 mV peak-topeak
eye diagram with 16 equalization levels and achieves a
remarkably low 2.25 pJ/bit total power consumption (0.633 pJ/bit
for the predriver+driver)
A Simple Simulation Approach for the Estimation of Convergence and Performance of Fully Adaptive Equalization in High-Speed Serial Interfaces
No full text
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Full text link“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
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