1,360,165 research outputs found
Who am I? Analysing Digital Personas in Cybercrime Investigations
No full textOnline cybercrime activities often involve criminals hiding behind multiple identities (so-called digital personas). Unraveling these multiple digital personas is a non-trivial problem owing to the large amounts of text communicated in online social media and the large numbers of digital personas involved. The cognitive load for cybercrime investigators is immense { existing tools lack the sophisticated capabilities required to analyse digital personas in order to provide investigators with clues to the identity of the individual or group hiding behind one or more personas. In this article, we present the Isis toolkit which addresses this very problem
Physical activity classification meeting daily life conditions
No full textPhysical activity is one of the key factors in determining the personal health and well-being of human beings in daily life conditions. Healthy ageing and physical activity has a strong association and ageing has become one of the highly concentrated area of research community in the past decade due to the expected increase in the elderly population. A statistical survey published by European Union (EU) in 2012 shows that the elderly population (over 65 years) of Europe, is expected to increase from 87.5 million to 152.6 million (65.1 million increase) during the period from 2010 to 2016 [1]. Physical inactivity and more sedentary life style can lead towards many chronic and life threatening diseases in older adults such as diabetes, cancer, cardiovascular and other lethal diseases. These damages can be controlled by performing various activities and vigorous exercises in daily life, in addition to medications to promote a healthier lifestyle [2]
Deep Learning-Based Phase Unwrapping and Image Denoising for 3D Reconstruction in Digital Holography and Photoacoustic Imaging
No full textFull-field optical and photoacoustic imaging systems—such as Digital Holography and Full-Field Photoacoustic Tomography (FF-PAT)—have become essential tools for non-invasive, high-resolution imaging in biomedical diagnostics and industrial inspection. These systems capture critical phase and displacement information necessary for 3D reconstruction and quantitative analysis. However, phase and displacement maps are often severely corrupted by speckle noise, Gaussian noise, and ambient interference, posing significant challenges for accurate signal recovery. Traditional denoising and unwrapping algorithms often fail under these harsh conditions due to their sensitivity to noise, assumptions about phase smoothness, and high computational costs. This thesis proposes three deep learning-based frameworks to address these challenges, offering robust, accurate, and efficient solutions for denoising and phase recovery in full-field imaging. Each framework is specifically tailored to overcome the limitations of conventional methods and to operate reliably under low- SNR conditions. First, we propose WPD-Net (Wrapped Phase Denoising Network), a lightweight neural network designed for denoising wrapped-phase images affected by complex noise mixtures. WPD-Net integrates Residual Dense Attention Blocks (RDABs) to selectively enhance important features while suppressing irrelevant noise. A growth-rate-based multi-scale feature expansion and dense feature fusion strategy are incorporated to preserve fine structural details and ensure phase continuity. Evaluations on both synthetic and experimental datasets demonstrate that WPD-Net outperforms traditional and deep learning- based denoising approaches in terms of PSNR, SSIM, and visual quality. Its compact design also enables real- time inference, making it highly suitable for biomedical and industrial optical systems where fast, accurate processing is critical. Next, to unify denoising and phase unwrapping into a single step, we introduce DenSFA- PU (Densely Connected Spatial Feature Aggregator for Phase Unwrapping). DenSFA-PU is an end-to-end regression model that directly maps noisy wrapped-phase inputs to unwrapped continuous outputs. The network combines dense connectivity with a Spatial Feature Aggregator (SFA) module, integrating Bi- directional LSTM layers and Bottleneck Attention Modules (BAMs) to capture long-range dependencies and focus on structurally important regions. Extensive experiments show that DenSFA-PU achieves superior results across standard evaluation metrics (PSNR, SSIM, NRMSE) and maintains fast inference times (~29.31 ms per image). This efficiency, combined with high robustness against severe noise, positions DenSFA-PU as a powerful tool for real-time and high-throughput phase imaging applications. Finally, for FF-PAT, we address displacement map denoising—a particularly challenging problem due to the extremely low SNR of photoacoustic signals. We propose an attention-guided, multi-scale feature fusion network that combines RDABs with dual channel and spatial attention modules. Trained exclusively on experimentally acquired FF- PAT data, the model demonstrates strong generalization to real-world noise conditions. It achieves a PSNR of 34.25 dB, significantly outperforming coherent averaging (13.88 dB) and U-Net-based approaches (26.87 dB). With a processing speed of 0.53 seconds per displacement map, the model enables real-time volumetric photoacoustic imaging while preserving critical structural information. ⓒ2025 Muhammad Awais ALL RIGHTS RESERVEDDoctorAbstract i
Contentsiii
List of Figures v
List of Tables viii
Chapter 1. Introduction 1
1.1 Motivation 1
1.2 Problem Statement 2
1.3 Contributions 3
1.4 Thesis structure 4
Chapter 2. Background and Related Work 5
2.1 Optical and Photoacoustic Imaging: Principles and Applications 5
2.2 Wrapped Phase and Unwrapping Problem 9
2.2.1 One-dimensional Phase Unwrapping 9
2.2.2 Two-dimensional Spatial Phase Unwrapping 11
2.3 Traditional Unwrapping Techniques 13
2.4 Denoising Wrapped Phase Images 16
2.5 Deep Learning in Phase Unwrapping- 18
2.6 Denoising Displacement Maps in FF-PAT 21
Chapter 3. Wrapped Phase Denoising Network- 24
3.1 Overview 24
3.2 Architecture of WPD-Net 25
3.2.1 Shallow Feature Extraction (SFE) Module- 25
3.2.2 Residual Dense Attention Blocks (RDABs) 25
3.2.3 Dense Feature Fusion (DFF) Module 28
3.3 Advantages of WPD-Net- 29
3.4 Loss Function 31
3.5 Training and Evaluation 32
3.5.1 Dataset Preparation 32
3.5.2 Training Parameters and Evaluation Metrics- 34
3.6 Experimental Results 38
3.6.1 Experiments with Synthetic Data 38
3.6.2 Experiments with Real Data- 44
3.7 Ablation Study- 49
3.8 Conclusions and Discussion 51
Chapter 4. DenSFA-PU Phase Unwrapping Network- 53
4.1 Overview 53
4.2 Architecture of DenSFA-PU 54
4.3 Loss Function 59
4.4 Training and Evaluation 60
4.4.1 Dataset Preparation 60
4.4.2 Training Parameters and Evaluation Metrics- 62
4.5 Experimental Results 66
4.5.1 Experiments with Synthetic Data 66
4.5.2 Experiments with Real Data- 80
4.6 Ablation Study- 83
4.7 Conclusions and Discussion 84
Chapter 5. Denoising in Full-Field Photoacoustic Tomography 87
5.1 Overview 87
5.2 Network Architecture for FF-PAT Displacement Map Denoising- 88
5.3 Loss Function 92
5.4 Experimental Results 92
5.4.1 Data Generation- 92
5.4.2 Results 94
5.5 Ablation Study- 98
5.6 Conclusions and Discussion 98
Chapter 6. Conclusions and Future Work 100
6.1 Conclusions 100
6.2 Future Work 102
References 105
Acknowledgement 116
Curriculum Vitae 11
Going Beyond Counting First Authors in Author Co-citation Analysis
No full textThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Visualization of Heliostat Field of Solar Thermal Tower Power Plant Using Virtual Reality (VR) Technologies
No full textAn important part of future global energy depends on the development of the solar industry.
To date, we have noticed the shift from fossil fuels energy towards renewable energy. The past decade
has shown significant progress in computer science, and CAD is increasingly used for design and
development. Visualization of the data generated from the models in the CAD program plays an
important role in the creation of state-of-the-art designs. An important limitation during the design
phase is the visualization of three-dimensional geometry. This article attempts to illustrate the use of
VR technologies in solar thermal power plant development. This article analyzes various strategies
and methods for the visualization of CAD models in virtual reality. Android phone interfaces with
a desktop computer, as well as head movement control strategies, are discussed. It is concluded
that VR technologies can help with visualization, as well as in the development of the field of solar
thermal power plants, having minimal design-related issues
Transactions on Aspect-Oriented Software Development IV
No full textVolume IV of Transactions on Aspect-Oriented Software Development continues the special issue on Early Aspects from volume III. The special issue was guest edited by João Araújo and Elisa Baniassad and handled by one of the co-editors-in-chief, Mehmet Aksit. The papers in volume III discussed topics pertaining to analysis, visualisation, conflict identification and composition of Early Aspects. The papers in this volume focus on mapping of Early Aspects across the software lifecycle. Complementing this focus on aspect mapping is a special section on Aspects and Software Evolution guest edited by Walter Cazzola, Shigeru Chiba and Gunter Saake—the co-editor-in-chief handling this issue was Awais Rashid
Multiple tuning curve based wideband RC VCO design / Muhammad Awais
No full textVoltage controlled Oscillator (VCO) is a key element in defining overall system specification. It is widely used in communication equipment as an essential part of frequency synthesizers and phase-locked loops (PLL). In achieving high tuning range performance an oscillator pays its penalty in degraded phase noise output. Resorting into a LC based VCO at high frequency which exhibit superior phase noise performance foresees large active area consumption with a proportional increase in the cost. The evolution of deep-submicron CMOS technology mandates the need of low power solution with a proportional headroom limitation. In view of the highlighted challenges, this work proposes a RC based Voltage Controlled Oscillator (RC-VCO) with programmable tuning curves to achieve a wideband frequency operation. Fabricated and characterized in 130 nm standard CMOS platform, the VCO switches between the tuning curves with a programmable current injection. The VCO exhibit a frequency operation between 2.05 to 4.19 GHz, resulting in a wideband tuning range of 68.5%. The proposed architecture consumes a maximum dc current of 8.8mA measured at the highest frequency of operation. The design also observes a phase noise of -99.3 dBc/Hz at an offset of 1MHz with a carrier of 4.19GHz. The proposed RC-VCO achieves a Figure of Merit of -161.4 dBc/Hz (FOM) and -178.1 dBc/Hz (FOMT), respectively. The summary of performance favours the architecture in the integration of a wideband frequency synthesizer
Design of advanced LDPC decoders using traditional and new implementation technologies
No full textLow Density Parity Check (LDPC) codes, a class of linear block codes have gained
huge attention in digital communication domain. Binary LDPC codes were invented
by Gallager in 1963 and rediscovered by Mackay and Neil in 1995. Thanks to near
Shannon limit performance, low error floor, intrinsic parallelism and affordable com-
plexity, binary LDPC codes are considered in a number of standards e.g. WiMAX
(IEEE 802.16e), WiFi (IEEE 802.11n), WLAN and DVB-S2. Non binary LDPC
(NB-LDPC) codes, an extension of binary LDPC to higher order Galois fields, show
better performance when the code length is small or when a high-order modula-
tion is applied in the communication system. Apart from all the elegant features,
hardware design of LDPC decoders meeting area, power and speed constraints is
still a challenging task and requires considerable research effort. In this thesis we
focused our research towards efficient design of high performance LDPC decoders
using traditional CMOS VLSI and “beyond CMOS” technologies. This thesis has
contributions both in the domain of binary and non binary LDPC decoding. The
main contributions to this thesis are summarized in the following paragraphs.
The processing core of a binary LDPC decoder lies in the check node (CN)
part which executes actual decoding algorithm and contributes towards the overall
complexity, throughput and performance of the whole decoder. The state of the art
for LDPC decoders mainly features a partial parallel architecture which consists of
a number of CNs realized in hardware to achieve flexible, high throughput, iterative
decoding. However, in most of the published works on LDPC decoders, the CN
itself is implemented in a serial way which limits the achievable throughput to a
large extent. Realizing high throughput decoders (supporting data rates up to few
hundred Mbps) either asks for a massive number of CNs or a high clock frequency
which results in significant area and power overhead. Parallelism at check node level
is an essential step which can bring significant increase in throughput. However, a
straightforward parallel implementation suffers from large complexity of CN. So,
in the first part of the thesis we proposed a generic implementation of a parallel
check node based on a novel “Tree way” approach. In addition, we presented a
generalization of the “Tree-way” approach for check node degree dc up to 32, which
provides compile time flexibility to support a large number of LDPC codes for next
generation standards. The “Tree way” check node architecture is exploited to design
a fully parameterized LDPC decoder IP core forWiMAX andWiFi standards. With
the help of an efficient datapath reuse and simple control mechanism, the proposed
decoder based on “Tree way” check node achieves a high throughput with fairly
affordable complexity.
The second part of the thesis deals with the the VLSI hardware implementation
of a novel Belief Propagation (BP) algorithm named as Analog Digital Belief Prop-
agation (ADBP). The ADBP algorithm works on factor graphs over linear models and uses messages in the form of Gaussian like probability distributions by track-
ing their parameters. In particular, ADBP can deal with system variables that are
discrete and/or wrapped. A variant of ADBP can then be applied for the iterative
decoding of a particular class of NB-LDPC codes and yields decoders with complex-
ity independent of modulation alphabet size M, thus allowing to construct efficient
decoders for digital transmission systems with unbounded spectral efficiency. In this
work, we propose some simplifications to the updating rules for ADBP algorithm
that are suitable for hardware implementation. In addition, we analyze the effect of
finite precision on the decoding performance of the algorithm. A careful selection of
quantization scheme for input, output and intermediate variables allows us to con-
struct a complete ADBP decoding architecture that performs close to the double
precision implementation and shows a promising complexity for large values of M.
Because of the computation intensive nature of LDPC decoding algorithms, a
CMOS VLSI based implementation of LDPC decoders results in a considerable area
and power. In addition, the limitations on the switching frequency of CMOS transis-
tors puts an upper bound on the achievable throughput. Therefore, implementation
of LDPC decoders on advanced “beyond CMOS” technologies makes sense. Quan-
tum dot Cellular Automata (QCA) is an emerging nanotechnology that has gained
significant research interest in recent years. Extremely small feature sizes, ultra low
power consumption, and high clock frequency make QCA a potentially attractive
solution for implementing computing architectures at the nanoscale. In the third
part of the thesis we present a novel QCA architecture for binary LDPC check node
which executes Normalized Min Sum algorithm. We adapt the decoding architec-
ture to the specific characteristics of QCA technology, by exploiting majority voting
circuits and inherent delaying and pipelining behavior of wires. The proposed CN is
fully pipelined, partial parallel and reconfigurable to support up to degree dc = 20.
The circuit is described using a realistic layout aware VHDL model which allows
in addition to the circuit simulation, area and power estimation for the two im-
plementations of QCA technology i.e. magnetic and molecular. Simulation results
show that remarkable area saving and high throughput could be achieved for molec-
ular QCA implementation, while the magnetic QCA is attractive for achieving low
power. For both cases, the proposed design has an area fairly smaller and clock
speed comparable or much larger than its implementation on up to date CMOS
technology. Finally, we present a QCA implementation of Fast Fourier Transform
(FFT) Algorithm which has application in decoding of non binary LDPC codes.
A novel architecture for a partial parallel FFT processor is presented which not
only reduces the circuit complexity but also eliminates the need of feedback signals,
allowing to maximize the throughput. Again, the circuit performance results are
estimated with the help of a layout aware VHDL model for magnetic and molecular
QCA technologies
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