3,049 research outputs found
Multiobjective Evolutionary Map Design for Cube 2: Sauerbraten
No full textMap design is a major challenge in the development of a successful multiplayer first-person shooter. In fact, it has a large impact on the game dynamics and deeply affects the player experience. In this paper, we present a search-based procedural content generation approach to the map design problem in Cube 2: Sauerbraten, an open-source first-person shooter. Extending previous works introduced in the literature, we propose several design objectives to evaluate the maps as well as a novel methodology to compute them. To test our approach, we designed two different design problems that require to deal with conflicting objectives (i.e., balancing, pacing, and achievement of long kill streaks) and with players using different playing styles. The results are promising as they show that our approach, exploiting multiobjective evolution, is able to explore effectively the map design space and to provide maps that feature interesting tradeoffs between the conflicting objectives
An assessment of the impact of possible CAP reform scenarios on Romanian agriculture
Full text linkUsing a simplified model, with key-variable the prices of two different possible scenarios of CAP reform after 2013 (moderate and radical), this paper present a comparison between the price effects of implementation of each reform scenario at 2015 horizon on Romanian agriculture. This short analysis shows that, under the presented hypotheses, the net welfare effect, due to the price changes, for the selected products, is positive in both reform scenarios, yet greater in the case of the radical reform. Integrated in the large context of Romanian development, it seems that the influence of CAP reform upon agriculture and rural areas will be most likely a gradual one: an interpenetration between the two scenarios is foreseeable, starting with the moderate reform that will dominate the period around 2013, the reform measures acquiring a more radical character afterwards.CAP reform, Romania, welfare effects, Agricultural and Food Policy,
Rich, Sturmian, and trapezoidal words
Full text linkIn this paper we explore various interconnections between rich words, Sturmian words, and trapezoidal words. Rich words, first introduced by the second and third authors together with J. Justin and S. Widmer, constitute a new class of finite and infinite words characterized by having the maximal number of palindromic factors. Every finite Sturmian word is rich, but not conversely. Trapezoidal words were first introduced by the first author in studying the behavior of the subword complexity of finite Sturmian words. Unfortunately this property does not characterize finite Sturmian words. In this note we show that the only trapezoidal palindromes are Sturmian. More generally we show that Sturmian palindromes can be characterized either in terms of their subword complexity (the trapezoidal property) or in terms of their palindromic complexity. We also obtain a similar characterization of rich palindromes in terms of a relation between palindromic complexity and subword complexity
Characterization Results for the Poset Based Representation of Topological Relations - I: Introduction and Models
No full text@article{DBLP:journals/informaticaSI/ForlizziN99,
author = {Luca Forlizzi and
Enrico Nardelli},
title = {Characterization Results for the Poset Based Representation
of Topological Relations - I: Introduction and Models.},
journal = {Informatica (Slovenia)},
volume = {23},
number = {2},
year = {1999},
bibsource = {DBLP, http://dblp.uni-trier.de}
Characterization Results for the Poset Based Representation of Topological Relations - II: Intersection and Union
No full text@article{DBLP:journals/informaticaSI/ForlizziN00,
author = {Luca Forlizzi and
Enrico Nardelli},
title = {Characterization Results for the Poset Based Representation
of Topological Relations - II: Intersection and Union.},
journal = {Informatica (Slovenia)},
volume = {24},
number = {1},
year = {2000},
bibsource = {DBLP, http://dblp.uni-trier.de}
Compiling higher-order specifications to SMT solvers : how to deal with rejection constructively
Full text linkModern verification tools frequently rely on compiling high-level specifications to SMT queries. However, the high-level specification language is usually more expressive than the available solvers and therefore some syntactically valid specifications must be rejected by the tool. In such cases, the challenge is to provide a comprehensible error message to the user that relates the original syntactic form of the specification to the semantic reason it has been rejected. In this paper we demonstrate how this analysis may be performed by combining a standard unification-based type-checker with type classes and automatic generalisation. Concretely, type-checking is used as a constructive procedure for under-approximating whether a given specification lies in the subset of problems supported by the solver. Any resulting proof of rejection can be transformed into a detailed explanation to the user. The approach is compositional and does not require the user to add extra typing annotations to their program. We subsequently describe how the type system may be leveraged to provide a sound and complete compilation procedure from suitably typed expressions to SMT queries, which we have verified in Agda
System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing
No full textThis dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications.
Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance.
This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB.
Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy).
The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption.
Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude
Vehicle: Bridging the Embedding Gap in the Verification of Neuro-Symbolic Programs (Invited Talk)
Full text linkNeuro-symbolic programs, i.e. programs containing both machine learning components and traditional symbolic code, are becoming increasingly widespread. Finding a general methodology for verifying such programs is challenging due to both the number of different tools involved and the intricate interface between the "neural" and "symbolic" program components. In this paper we present a general decomposition of the neuro-symbolic verification problem into parts, and examine the problem of the embedding gap that occurs when one tries to combine proofs about the neural and symbolic components. To address this problem we then introduce Vehicle - standing as an abbreviation for a "verification condition language" - an intermediate programming language interface between machine learning frameworks, automated theorem provers, and dependently-typed formalisations of neuro-symbolic programs. Vehicle allows users to specify the properties of the neural components of neuro-symbolic programs once, and then safely compile the specification to each interface using a tailored typing and compilation procedure. We give a high-level overview of Vehicle’s overall design, its interfaces and compilation & type-checking procedures, and then demonstrate its utility by formally verifying the safety of a simple autonomous car controlled by a neural network, operating in a stochastic environment with imperfect information
A General Formulation to Describe Empirical Rainfall Thresholds for Landslides
Full text linkAbstractIn this paper, a brief description of the Generalized FLaIR Model (GFM, De Luca and Versace, 2016) is provided, that is able to reproduce all the empirical thresholds proposed in literature, aimed to forecast landslides triggered by rainfall. In particular, this paper focuses on Antecedent Precipitation (AP) schemes. The paper demonstrates that these are particular solutions of the GFM and will exemplify this using AP schemes for NE Italy1, Seattle2 and Nicaragua - El Salvador3
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