336 research outputs found
Integration, Commissioning and First Experience of ALICE ITS Control and Readout Electronics
No full textFor the third running period of the CERN LHC, the ALICE experiment will undertake several upgrades of its sub-detectors. One of the detectors to be upgraded is the Inner Tracking System, featuring the new ALPIDE pixel chip. Control and readout of the 24120 chips are handled by 192 custom FPGA-based readout units. Each readout unit can forward 9.6 Gbps of data to another custom PCIe card that aggregates the data from several units and transmits it for further offline/online analysis. Integration and commissioning of the system is underway and this paper describes the first experiences and results of this effort
Upgrades of the ALICE TPC Front-End Electronics for Long Shutdown 1 and 2
No full textThis paper presents the front-end electronics upgrades of the ALICE Time Projection Chamber detector for the coming years, with a focus on the upgrades for Long Shutdown 2. The Large Hadron Collider is currently in Long Shutdown 1 following a successful first run, and upgrades of the detectors are underway to support the higher particle interaction rates planned for the next run. For the Time Projection Chamber, the increase in data due to the higher interaction rate and higher energy will cause a bottleneck in the Readout Control Unit and a new board is in development which increases the data-link speed to the back-end. Another more general upgrade of the ALICE experiment is planned for Long Shutdown 2, foreseen to start in 2018. In this case the goal is to cope with an even higher interaction rate of 50 kHz for Pb-Pb collisions. The present Multi Wire Proportional Chambers of the Time Projection Chamber will then be replaced by Gas Electron Multiplier technology. At the same time, the front-end electronics and readout system will also be replaced
Design, Verification and Testing of a Digital Signal Processor for Particle Detectors
No full textThe A Large Ion Collider Experiment (ALICE) at the Large Hadron Collider at CERN is upgrading two of its sub-detectors, the Time Projection Chamber and Muon Chambers, with new front-end electronics to handle the expected higher Pb–Pb collision-rates in the next running period (Run 3) foreseen to start in 2021. The higher collision rate requires the detectors to employ a continuous readout of the data from the front-end, in contrast to the previous triggered readout. The devices currently employed for the readout of the detectors can only operate in triggered mode and need to be replaced. A new 32-channel integrated circuit called SAMPA has been designed to match the requirements of both detectors. The SAMPA device contains a charge sensitive amplifier, a pulse shaper, and a 10-bit 10MHz analogue to digital converter for each channel and a common digital signal processor part. The digital signal processor provides various signal filtering and conditioning operations to improve on the data compression ability. Acquisition can be done in either triggered or continuous mode and the data is offloaded through 320 Mbps differential serial links, allowing a data throughput of up to 3.2 Gbps. The first prototype of the SAMPA was delivered in 2014, the second in 2016 and the third was delivered in end of 2017. The final production run was done in mid- 2018 and completed the testing at the end of 2018. Front-End Card production and testing is underway and the Muon Tracking Chamber (MCH) and Time Projection Chamber (TPC) are ready for installation in mid-2019. The main purpose of this thesis has been to specify, design, test and verify the digital signal processing part of the SAMPA device to encompass the needs of the detectors involved. Innovative solutions have been employed to reduce the bandwidth required by the detectors, as well as adaptations to ease data handling later in the processing chain. By means of simulations, test procedures, verification methods and applied methods for design of reliable systems, a major part of the work has been on qualifying the design for submission to production. Since the design submission process and the following production time of the device is quite long and as the only means of verifying and reading out data from the analogue front-end and the analogue to digital converter is through the digital part of the device, it is of the essence to have a complete functioning prototype of the digital design before submission. A high-speed data acquisition system was developed to enable test and verification of the produced devices. It has been used in all facets of qualification of the device for use by the detectors. Three rounds of prototypes have been produced and tested. Only minor modifications to the digital design were added between the second and third prototype. The final production of about 80 000 devices has been completed with the same design as for the third prototype. No major issues have been found in the final design. The design and test features implemented in the design have been utilized in the production testing and a final yield of close to 80% have been reached
Design, implementation and testing of SRAM based neutron detectors
No full textNeutrons of thermal and high energies can change the value of a bit stored in a Static Random Access Memory (SRAM) memory chip. The effect is non destructive and linearly dependent on the amount of incoming particles, which makes it exploitable for use as a neutron detector. Detection is done by writing a known pattern to the memory and continuously reading it back checking for wrong values. As the SRAM memory is immune to gamma radiation it is ideal for use in for instance medical linear accelerators for detection of neutron dose to a patient. The intention of this work has been twofold: (1) Testing of different SRAM devices of different bit-sizes, manufacturers, feature sizes and voltages for their sensitivity to neutrons of different energies from thermal to high energies. (2) Design and implement detector hardware, firmware and its accompanying readout system for successful use in irradiation testing. The work has been done in close collaboration with Eivind Larsen, whose main contributions has been related to the nuclear physics aspect of the work in addition to arrangements in regard to beam setup and experimentation. Testing have been done at the Physikalisch-Technische Bundesanstalt (PTB) facility in Braunschweig Germany in a quasi-monochromatic neutron beam of 5:8MeV, 8:5MeV and 14:8MeV, finding a dependence of the sensitivity on the energy. In addition there have been testing conducted in the high energy hadron field at CERF at CERN, finding that by using the results from the other experiments an estimated range of the saturation cross section could be determined. Testing was also conducted at two occasions in the 29MeV proton beam at Oslo Cyclotron Laboratory (OCL) in Oslo Norway, where it was found that the detector could be used as a reference detector for beam monitoring and for beam profile characterization. The cross sections of the detectors were found to be comparable to the 14:8MeV cross section found at PTB. Thermal neutron testing of the devices was done in the thermal neutron field of the nuclear reactor at Institute for Energy Technology (IFE) at Kjeller Norway. All the devices were found to be sensitive to the field. Detector electronics, adapted to the different devices, has been built which can withstand the same radiation as the memory device without malfunctioning. There has been a focus on using Commercial Off The Shelf (COTS) components for reducing the total cost of the detector to about 100-200$US. The use of COTS SRAM memory devices also simplifies the reproducibility and availability of spares. The detector currently uses a two way communication between the detector and iv Abstract the readout computer over two pair of cables reducing the amount of cabling needed for experiments. The detectors can be connected to the communication link in a bus fashion, currently enabling a total of 14 detectors to be tested simultaneously from 100m away, over the same cable. Single Event Latch-up (SEL) and problems with irregular count rate of SRAMs created in the 90nm fabrication node has created problems during testing. Some solutions and techniques to mitigate these in hardware and firmware are presented in this work.Master i FysikkMAMN-PHYSPHYS39
Design, implementation and testing of SRAM based neutron detectors
No full textNeutrons of thermal and high energies can change the value of a bit stored in a Static Random Access Memory (SRAM) memory chip. The effect is non destructive and linearly dependent on the amount of incoming particles, which makes it exploitable for use as a neutron detector. Detection is done by writing a known pattern to the memory and continuously reading it back checking for wrong values. As the SRAM memory is immune to gamma radiation it is ideal for use in for instance medical linear accelerators for detection of neutron dose to a patient. The intention of this work has been twofold: (1) Testing of different SRAM devices of different bit-sizes, manufacturers, feature sizes and voltages for their sensitivity to neutrons of different energies from thermal to high energies. (2) Design and implement detector hardware, firmware and its accompanying readout system for successful use in irradiation testing. The work has been done in close collaboration with Eivind Larsen, whose main contributions has been related to the nuclear physics aspect of the work in addition to arrangements in regard to beam setup and experimentation. Testing have been done at the Physikalisch-Technische Bundesanstalt (PTB) facility in Braunschweig Germany in a quasi-monochromatic neutron beam of 5:8MeV, 8:5MeV and 14:8MeV, finding a dependence of the sensitivity on the energy. In addition there have been testing conducted in the high energy hadron field at CERF at CERN, finding that by using the results from the other experiments an estimated range of the saturation cross section could be determined. Testing was also conducted at two occasions in the 29MeV proton beam at Oslo Cyclotron Laboratory (OCL) in Oslo Norway, where it was found that the detector could be used as a reference detector for beam monitoring and for beam profile characterization. The cross sections of the detectors were found to be comparable to the 14:8MeV cross section found at PTB. Thermal neutron testing of the devices was done in the thermal neutron field of the nuclear reactor at Institute for Energy Technology (IFE) at Kjeller Norway. All the devices were found to be sensitive to the field. Detector electronics, adapted to the different devices, has been built which can withstand the same radiation as the memory device without malfunctioning. There has been a focus on using Commercial Off The Shelf (COTS) components for reducing the total cost of the detector to about 100-200$US. The use of COTS SRAM memory devices also simplifies the reproducibility and availability of spares. The detector currently uses a two way communication between the detector and iv Abstract the readout computer over two pair of cables reducing the amount of cabling needed for experiments. The detectors can be connected to the communication link in a bus fashion, currently enabling a total of 14 detectors to be tested simultaneously from 100m away, over the same cable. Single Event Latch-up (SEL) and problems with irregular count rate of SRAMs created in the 90nm fabrication node has created problems during testing. Some solutions and techniques to mitigate these in hardware and firmware are presented in this work
- …
