59 research outputs found
Potenziale von Large Language Models zur Unterstützung der Modellierung von Simulationseingabedaten
No full textThe simulation of complex systems, for example in production and logistics, is essential for the planning and control of such systems. A key aspect of this is the modeling of input data, as the quality of the results depends heavily on the accuracy of this data. However, conventional methods are often complex, error-prone and require in-depth specialist knowledge. Large language models (LLMs) offer new potential for automation, as they are able to analyze complex data and process it in natural language. This article examines if and to what extent LLMs can improve and support the process of simulation input data modeling
Potenziale von Large Language Models zur Unterstützung der Modellierung von Simulationseingabedaten
No full textThe simulation of complex systems, for example in production and logistics, is essential for the planning and control of such systems. A key aspect of this is the modeling of input data, as the quality of the results depends heavily on the accuracy of this data. However, conventional methods are often complex, error-prone and require in-depth specialist knowledge. Large language models (LLMs) offer new potential for automation, as they are able to analyze complex data and process it in natural language. This article examines if and to what extent LLMs can improve and support the process of simulation input data modeling
Improved coupling based wide pass-band filter with double square complementary split ring resonator
No full textHeat Transfer Modification in a Particle-Laden Turbulent Channel Flow: For externally heated particles
No full textHeat transfer in multiphase flows plays an important role in many industrial applications. For instance, particle-based solar receivers utilize the high absorptivity and heat capacity of dispersed phase in a carrier fluid to improve efficiency and heat transfer. This dispersed phase generally consists of a large number of small particles. It is, therefore, difficult to completely resolve such flows considering their finite size. Usually, these particles are so small, that they can be treated as point particles. This considerably reduces the computational effort, while preserving the essential characteristics of the particle-laden flows. In this thesis, the focus is on heat transfer modulation in a particle-laden turbulent channel flow using direct numerical simulations. In flows with temperature gradients (for example, channel flow between hot and cold wall), particles absorb heat from hotter regions and release heat to colder regions, thereby enhancing heat transfer through particle feedback flux. On the other hand, presence of particles leads to decay in turbulence resulting in lower turbulent heat transfer. The interplay of this two phenomena can either increase or decrease the overall heat transfer based on Stokes number and thermal Stokes number (ratio of thermal response time to characteristic time scale of the flow).To investigate the heat transfer modulation in particle-laden channel flow, the existing DNS code developed by Boersma [5] has been modified to include particle transport and heat transfer. The point-particle approach with two way coupling is implemented using trilinear interpolation scheme and 3 rd order Runge-Kutta time marching scheme. The implemented code is validated using the results from literature [20] for a flow with no external heating.With the developed code, cases with no external source term and external source term with different optical thickness of the fluid have been analyzed. In order to focus only on the fluid-particle interaction, the effect of gravity is neglected and the flow is considered to be incompressible. It has been observed from these simulations that particles play an important role in modulation of heat transfer in such flows. Mean temperature profiles, heat flux mechanisms, temperature variance and budgets of temperature variance are studied extensively in order to understand the underlying phenomenon. It is found that the particle feedback heat transfer is the dominating mode in particle-laden flows
GemV: A Validated Micro-architecture Vulnerability Estimation Tool
No full textabstract: Several decades of transistor technology scaling has brought the threat of soft errors to modern embedded processors. Several techniques have been proposed to protect these systems from soft errors. However, their effectiveness in protecting the computation cannot be ascertained without accurate and quantitative estimation of system reliability. Vulnerability -- a metric that defines the probability of system-failure (reliability) through analytical models -- is the most effective mechanism for our current estimation and early design space exploration needs. Previous vulnerability estimation tools are based around the Sim-Alpha simulator which has been to shown to have several limitations. In this thesis, I present gemV: an accurate and comprehensive vulnerability estimation tool based on gem5. Gem5 is a popular cycle-accurate micro-architectural simulator that can model several different processor models in close to real hardware form. GemV can be used for fast and early design space exploration and also evaluate the protection afforded by commodity processors. gemV is comprehensive, since it models almost all sequential components of the processor. gemV is accurate because of fine-grain vulnerability tracking, accurate vulnerability modeling of squashed instructions, and accurate vulnerability modeling of shared data structures in gem5. gemV has been thoroughly validated against extensive fault injection experiments and achieves a 97\% accuracy with 95\% confidence. A micro-architect can use gemV to discover micro-architectural variants of a processor that minimize vulnerability for allowed performance penalty. A software developer can use gemV to explore the performance-vulnerability trade-off by choosing different algorithms and compiler optimizations, while the system designer can use gemV to explore the performance-vulnerability trade-offs of choosing different Insruction Set Architectures (ISA).Dissertation/ThesisMasters Thesis Computer Science 201
Crossroads --- A Time-Sensitive Autonomous Intersection Management Technique
No full textabstract: For autonomous vehicles, intelligent autonomous intersection management will be required for safe and efficient operation. In order to achieve safe operation despite uncertainties in vehicle trajectory, intersection management techniques must consider a safety buffer around the vehicles. For truly safe operation, an extra buffer space should be added to account for the network and computational delay caused by communication with the Intersection Manager (IM). However, modeling the worst-case computation and network delay as additional buffer around the vehicle degrades the throughput of the intersection. To avoid this problem, AIM, a popular state-of-the-art IM, adopts a query-based approach in which the vehicle requests to enter at a certain arrival time dictated by its current velocity and distance to the intersection, and the IM replies yes/no. Although this solution does not degrade the position uncertainty, it ultimately results in poor intersection throughput. We present Crossroads, a time-sensitive programming method to program the interface of a vehicle and the IM. Without requiring additional buffer to account for the effect of network and computational delay, Crossroads enables efficient intersection management. Test results on a 1/10 scale model of intersection using TRAXXAS RC cars demonstrates that our Crossroads approach obviates the need for large buffers to accommodate for the network and computation delay, and can reduce the average wait time for the vehicles at a single-lane intersection by 24%. To compare Crossroads with previous approaches, we perform extensive Matlab simulations, and find that Crossroads achieves on average 1.62X higher throughput than a simple VT-IM with extra safety buffer, and 1.36X better than AIM.Dissertation/ThesisMasters Thesis Engineering 201
STL on Limited Local Memory (LLM) Multi-core Processors
No full textabstract: Limited Local Memory (LLM) multicore architectures are promising powerefficient architectures will scalable memory hierarchy. In LLM multicores, each core can access only a small local memory. Accesses to a large shared global memory can only be made explicitly through Direct Memory Access (DMA) operations. Standard Template Library (STL) is a powerful programming tool and is widely used for software development. STLs provide dynamic data structures, algorithms, and iterators for vector, deque (double-ended queue), list, map (red-black tree), etc. Since the size of the local memory is limited in the cores of the LLM architecture, and data transfer is not automatically supported by hardware cache or OS, the usage of current STL implementation on LLM multicores is limited. Specifically, there is a hard limitation on the amount of data they can handle. In this article, we propose and implement a framework which manages the STL container classes on the local memory of LLM multicore architecture. Our proposal removes the data size limitation of the STL, and therefore improves the programmability on LLM multicore architectures with little change to the original program. Our implementation results in only about 12%-17% increase in static library code size and reasonable runtime overheads.Dissertation/ThesisM.S. Computer Science 201
Register File Organization for Coarse-Grained Reconfigurable Architectures: Compiler-Microarchitecture Perspective
No full textabstract: Coarse-Grained Reconfigurable Architectures (CGRA) are a promising fabric for improving the performance and power-efficiency of computing devices. CGRAs are composed of components that are well-optimized to execute loops and rotating register file is an example of such a component present in CGRAs. Due to the rotating nature of register indexes in rotating register file, it is very challenging, if at all possible, to hold and properly index memory addresses (pointers) and static values. In this Thesis, different structures for CGRA register files are investigated. Those structures are experimentally compared in terms of performance of mapped applications, design frequency, and area. It is shown that a register file that can logically be partitioned into rotating and non-rotating regions is an excellent choice because it imposes the minimum restriction on underlying CGRA mapping algorithm while resulting in efficient resource utilization.Dissertation/ThesisMasters Thesis Computer Science 201
Enabling Multi-threaded Applications on Hybrid Shared Memory Manycore Architectures
No full textabstract: As the number of cores per chip increases, maintaining cache coherence becomes prohibitive for both power and performance. Non Coherent Cache (NCC) architectures do away with hardware-based cache coherence, but they become difficult to program. Some existing architectures provide a middle ground by providing some shared memory in the hardware. Specifically, the 48-core Intel Single-chip Cloud Computer (SCC) provides some off-chip (DRAM) shared memory some on-chip (SRAM) shared memory. We call such architectures Hybrid Shared Memory, or HSM, manycore architectures. However, how to efficiently execute multi-threaded programs on HSM architectures is an open problem. To be able to execute a multi-threaded program correctly on HSM architectures, the compiler must: i) identify all the shared data and map it to the shared memory, and ii) map the frequently accessed shared data to the on-chip shared memory. This work presents a source-to-source translator written using CETUS that identifies a conservative superset of all the shared data in a multi-threaded application and maps it to the shared memory such that it enables execution on HSM architectures.Dissertation/ThesisMasters Thesis Computer Science 201
Construction of GCCFG for Inter-procedural Optimizations in Software Managed Manycore (SMM)
No full textabstract: Software Managed Manycore (SMM) architectures - in which each core has only a scratch pad memory (instead of caches), - are a promising solution for scaling memory hierarchy to hundreds of cores. However, in these architectures, the code and data of the tasks mapped to the cores must be explicitly managed in the software by the compiler. State-of-the-art compiler techniques for SMM architectures require inter-procedural information and analysis. A call graph of the program does not have enough information, and Global CFG, i.e., combining all the control flow graphs of the program has too much information, and becomes too big. As a result, most new techniques have informally defined and used GCCFG (Global Call Control Flow Graph) - a whole program representation which captures the control-flow as well as function call information in a succinct way - to perform inter-procedural analysis. However, how to construct it has not been shown yet. We find that for several simple call and control flow graphs, constructing GCCFG is relatively straightforward, but there are several cases in common applications where unique graph transformation is needed in order to formally and correctly construct the GCCFG. This paper fills this gap, and develops graph transformations to allow the construction of GCCFG in (almost) all cases. Our experiments show that by using succinct representation (GCCFG) rather than elaborate representation (GlobalCFG), the compilation time of state-of-the-art code management technique [4] can be improved by an average of 5X, and that of stack management [20] can be improved by an average of 4X.Dissertation/ThesisMasters Thesis Computer Science 201
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