1,720,956 research outputs found
Run-time Adaptable VLIW Processors: Resources, Performance, Power Consumption, and Reliability Trade-offs
No full textIn this dissertation, we propose to combine programmability with reconfigurability by implementing an adaptable programmable VLIW processor in a reconfigurable hardware. The approach allows applications to be developed at high-level (C language level), while at the same time, the processor organization can be adapted to the specific requirements (both static and dynamic) of different applications. Our proposed customizable VLIW processor called ?-VEX can be adapted at design-time as well as at run-time. Its instruction set architecture (ISA) is based on the VEX ISA and a toolchain (parametrized C compiler and simulator) is publicly available from Hewlett Packard (HP) for architectural exploration and code generation. The design-time parameters include the processor’s issue-width, the type of different functional units (FUs) and their latencies, the type and size of multiported register files, degree of pipelining, size of instruction and data memories, type of interrupt and exception systems, selection of default custom operations, datapath sharing. If the behavior of applications is not known at design-time or an application has different phases with distinct requirements, a fixed processor may not perform efficiently for all the applications/phases. To this end, we propose a run-time reconfigurable processor that can adapt its organization dynamically during execution. The run-time parameters include the processor’s issue-width, the type and number of different FUs, and the register file size. Additionally, we propose configurable fault tolerance techniques for the ?-VEX processor. The designer can choose to include or exclude the fault tolerance in the processor at design-time. When the fault tolerance is included, it can be made permanently enabled or enabled/disabled at run-time. All these options enable users to trade-off between hardware area/resources, performance, power/energy consumption, and reliability. The processor is available as open-source.Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Acceleration of Fingerprint Minutiae Extraction Using a VLIW Processor
No full textDeze scriptie beschrijft het ontwerp van een embedded systeem dat de kenmerkende eigenschappen uit de afbeelding van een vingerafdruk haalt. Het betreft een hardware/software codesign, waarbij een VLIW-processor als accelerator is gebruikt.Computer EngineeringMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Interrupt support on the ?-VEX processor
No full textIn this thesis, we present a design of interrupt system upon an extensible and reconfigurable VLIW softcore processor: r-VEX. This interrupt system is designed and implemented in four mechanisms to match different application requirements in terms of the hardware consumption and performance issues (interrupt latency). On the other hand, due to the fact that the VEX compiler is not an open-source compiler, extra requirements to the assembler are also considered to make our work feasible. Our interrupt system itself can also be parameterized to fit different applications. These parameters include the number of interrupt vectors, interrupt priority of each vector and Interrupt Service Routines (ISRs) location address in the instruction memory. The testing results show that each version of our interrupt system takes reasonable amount of hardware usage. We implemented our interrupt system on a virtex-6 FPGA. Besides, the interrupt latency can be reduced to only 2 clock cycles which is even better than some RISC-based softcore processors like Microblaze. This project creates a prototype of interrupt system that could work on VLIW softcore processor which extends the functionality and capability of the processor such as running operating systems and establishing a multi-core system.Embedded SystemsMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Fingerprint Verification on the VEX Processor
No full textThe speed gap between a processor realized in Semi-custom ASIC technology and a processor realized in FPGA technology is narrowing. In processor design, the approach is to define the microarchitecture of the processor and to design and implement it for executing an application domain. In this thesis, we have investigated the approach to design a customized and parametrized VLIW processor, such that it becomes better suited for imaging applications. We analyzed the requirement of a fingerprint application. Porting the application to the VEX simulator required design and integration of an arithmetic module for emulating 64-bit arithmetic. Subsequently, the application was ported to the VEX simulator such that we could derive the set of architectural parameters for the VEX processor. Based on these parameters, we designed a pipelined and scalable VLIW processor according to the VEX ISA. Moreover, the design of the processor was implemented and realized in a Virtex-VI FPGA. Furthermore, to create the instruction memory for the VEX processor, the required toolchain was developed from the inherited development framework of the r-VEX project. For this purpose, we extended the back-end of the VEX compiler, re-designed the assembler, integrated the linker and the loader. The resulting toolchain allowed us to extract and execute the fingerprint application's bottleneck and three other benchmarks, on the VEX processor. Compared to the inherited development framework, the re-designed toolchain is more mature and better to utilize, as it is able to create the instruction ROM for the VEX processor. The Fibonacci benchmark results showed that the VEX processor is 3.32 times faster than the original multi-cycle r-VEX processor. Moreover, the results of three other benchmark indicate that our designed processor is able to execute a range of applications.Master of Science Computer EngineeringMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Going Beyond Counting First Authors in Author Co-citation Analysis
Get PDFThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Get PDF“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Get PDFWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
Dispelling the Myths Behind First-author Citation Counts
Get PDFWe conducted a full-scale evaluative citation analysis study of scholars in the XML research field to explore just how different from each other author rankings resulting from different citation counting methods actually are, and to demonstrate the capability of emerging data and tools on the Web in supporting more realistic citation counting methods. Our results contest some common arguments for the continued
use of first-author citation counts in the evaluation of scholars, such as high correlations between author rankings by first-author citation counts and other citation
counting methods, and high costs of using more realistic citation counting methods that are not well-supported by the ISI databases. It is argued that increasingly available digital full text research papers make it possible for citation analysis studies to go beyond what the ISI databases have directly supported and to employ more
sophisticated methods
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