1,720,959 research outputs found
Single event transient reliability analysis on a fault-tolerant RISC-V microprocessor design
No full textThe miniaturization of electronic devices and the improved operating speeds increase the likelihood of single event faults. Differently from Single Event Upset (SEU) faults, Single Event Transient (SET) faults generally affect combinational logic, making all voting systems vulnerable to errors. The proposed work uses an ad-hoc fault-simulation campaign employing signal glitching to identify SET vulnerabilities inside a RISC-V core already equipped with resilience logic against Single Event Upset (SEU) faults. The faults target the majority voting logic structures, highlighting how they can be susceptible to faults depending on the width of the injected pulses, and showing how the use of Buffered Triple Modular Redundancy (BTMR) allows decreasing the total failure probability due to erroneous majority voters. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2024
Implementation of dynamic acceleration unit exchange on a RISC-V soft-processor
No full textUsing Artificial Intelligence (AI) techniques has become the best solution in many applications. By the end of Moore's Law, implementing a platform capable of such massive processing for edge-IoT applications has become a significant challenge. However, using static hardware accelerators can be an excellent solution; even so, they typically require a great deal of silicon area and are not optimized for all operation modes. Reconfigurable computing lets parts of the hardware change proportionally to the task during operation, allowing for optimized operation and the use of many hardware accelerators without requiring a large area. In this study, we present a dynamic acceleration unit exchange on a RISC-V soft-processor based on the open-source Klessydra-T13 RISC-V core. We show how reconfiguration can be used to make the hardware accelerator more flexible and improve its performance. As a case study, we show how reconfiguration techniques can be used to speed up AI architectures by reconfiguration of vector accelerator units
A universal hardware emulator for verification IPs on FPGA: a novel and low-cost approach
No full textEfficient and cost-effective functional verification strategies are more and more essential in digital integrated system design. This paper presents a low-cost approach to meet this challenge, introducing a universal hardware emulator designed for verifying various Intellectual Property (IP) cores on FPGA. We demonstrate the practicality and performance of this emulator through a use-case of verifying an advanced Integer Arithmetic Logic Unit (ALU) for the RISC-V ISA vector extension.
The process of integration and the results obtained from the verification are presented and discussed. Preliminary findings indicate that the emulator can perform more than 1.1 million tests per second. This research contributes to the advancement of hardware verification techniques, providing researchers, universities, and small businesses with an accessible and effective solution
Contextual bandits algorithms for reconfigurable hardware accelerators
No full textReconfigurable processing cores for IoT and edge computing applications are emerging topics to calibrate costs, energy consumption and area occupation with performance and reliability on Commercial Off the Shelf (COTS) devices. This work analyzes how to take advantage of Machine Learning to potentially automate the reconfiguration process of a hardware accelerator inside the Klessydra Vector Coprocessor Unit (VCU), choosing the best configuration according to the workload. The problem is modeled with a contextual bandits approach using the Linear UCB algorithms and validated with offline Python simulations
Dynamic triple modular redundancy in interleaved hardware threads: an alternative solution to lockstep multi-cores for fault-tolerant systems
Get PDFOver the years, significant work has been done on high-integrity systems, such as those found in cars, satellites and aircrafts, to minimize the risk that a logic fault causes a system failure, thus having functional safety as a key requirement. In this study, we employ an innovative approach to harness the benefits of both Dual Modular Redundancy and Triple Modular Redundancy techniques within an Interleaved-Multi-Threading microprocessor core, by means of a microarchitecture design capable of dynamically switching from Dual Modular Redundancy to Triple Modular Redundancy in case of faults. We explain the quantitative results obtained from an extensive fault injection simulation campaign on the fault tolerant core compared with its previous version regarding fault tolerant capabilities. The results show that in several application cases the fault resilience improvement and the hardware and timing overhead are better compared to the lockstep-based dual core approach. The proposed technique achieves 98,6% fault mitigation at the expense of only 4 clock cycles for roll-back overhead, with no checkpointing redundancy
Going Beyond Counting First Authors in Author Co-citation Analysis
Get PDFThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Get PDF“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Get PDFWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
Dispelling the Myths Behind First-author Citation Counts
Get PDFWe conducted a full-scale evaluative citation analysis study of scholars in the XML research field to explore just how different from each other author rankings resulting from different citation counting methods actually are, and to demonstrate the capability of emerging data and tools on the Web in supporting more realistic citation counting methods. Our results contest some common arguments for the continued
use of first-author citation counts in the evaluation of scholars, such as high correlations between author rankings by first-author citation counts and other citation
counting methods, and high costs of using more realistic citation counting methods that are not well-supported by the ISI databases. It is argued that increasingly available digital full text research papers make it possible for citation analysis studies to go beyond what the ISI databases have directly supported and to employ more
sophisticated methods
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