330 research outputs found
State Based Paxos
No full textPaxos is an algorithm that provides an elegant and optimal solution to the consensus problem in distributed systems. Despite its conceptual simplicity, industrial strength and high performance implementations of Paxos are very hard. This paper presents and evaluates the performance of State Paxos, a novel variation of the Paxos consensus algorithm that exploits overwrite semantics to eliminate most of the complexities and inefficiencies introduced by state management. This variation is suitable in applications where the current state depends only on the last update as opposed to the entire history, such as group management and distributed key-value stores. © 2013 ACM
Monte Carlo simulations of Fully Depleted CMOS pixel sensors for radiation detection applications
No full textThe ARCADIA (Advanced Readout CMOS Architectures with Depleted Integrated sensor Arrays) collaboration has developed 25 μm pitch Fully Depleted Monolithic Active Pixel Sensors (MAPS) based on a modified 110 nm CMOS
process in collaboration with LFoundry. This work illustrates a set of simulations performed on this detector technology, with the aim of investigating its capabilities for radiation detection applications. Three-dimensional Technology Computer Aided Design (TCAD) simulations have been performed in order to extract the electric field and electrostatic potential maps suitable to execute Monte Carlo simulations, providing high statistics of particle-sensor interaction in a reasonable computing time. The simulation flow will be described in detail and the main results will be pointed out
A 64-channel waveform sampling ASIC for SiPM in space-born applications
No full textThe architecture of a 64-channel ASIC for the readout of Silicon Photomultipliers in
space experiments is described. Each channel embeds a front-end amplifier with a common gate13 topology followed by a 256 cells analogue memory with a sampling frequency of 200 MHz. A14 single memory cell includes a storage capacitor, a single-slope Analog-to-Digital Converter (ADC)15 with programmable resolution between 8 and 12 bits and the digital control logic. To save power, the A/D conversion is carried-out only when a trigger signal is received. The trigger can either be generated inside the ASIC or provided by an external source.The analogue samples are digitized in parallel, thus reducing the conversion dead time. The memory cells can be arranged in a single array.
or they can be grouped in shorter slots of 32 or 64 cells that work in a multi-buffer configuration.20
The channels can work independently or they can be synchronised to acquire the same time-frame21
in the full chip. The target power consumption is 5 mW/channel. The ASIC is being designed in a22
65-nm CMOS technology. A digital-on-top flow is applied for the integration and final validation23
of the chip. The tape-out is scheduled in the first quarter of 202
A 28-nm CMOS pixel read-out ASIC for real-time tracking with time resolution below 20 ps
No full textWe present the development of a test ASIC, named Timespot1, designed in CMOS 28-nm technology, featuring a 32x32 pixel matrix and a pitch of 55 μm, The ASIC is conceived as the first prototype in a series, capable to read-out pixels with timing capabilities in the range of 30 ps and below. Each pixel is endowed with a charge amplifier, a discriminator and a Time-to-Digital-Converter, capable of time resolutions below 20 ps and read-out rates (per pixel) around 3 MHz. The timing performance are obtained respecting a power budget of about 50 μW per pixel, corresponding to a power density of approximately 2 W/cm 2 · This feature makes the Timespot1 approach an interesting solution for vertex detectors of the next generation of colliders, where high space and time resolutions will be mandatory requirements to cope with the huge amount of tracks per event to be detected and processed
New development on digital architecture for efficient pixel readout ASIC at extreme hit rate for hep detectors at HL-LHC
No full textA novel region-based pixel digital architecture for latency buffering and trigger matching able to withstand extended trigger latencies and unprecedented data rates at the High-Luminosity LHC upgrade is presented. The architecture features above 99.5% efficiency at nominal 3 GHz/cm 2 pixel hit rate and 1 MHz trigger rate with 12.5 μs trigger latency foreseen at HL-LHC. The overall inefficiency is dominated by dead-time in analogue front-end channels. The digital architecture is organized in pixel regions composed of 4×4 pixels. Charge information is retrieved from each pixel by means of Time-over-Threshold (ToT) using 5-bit counters. A common digital logic shared among pixels stores hits information for the whole trigger latency, handles the local configuration, performs trigger matching and sends zero-suppressed hit data to the chip periphery upon a trigger request. Data compression based on priority queues has been introduced in order to save area and power in the pixel region. The logic has been implemented in a commercial 65 nm CMOS pixel ASIC demonstrator prototyped as part of the Italian INFN CHIPIX65 project. Design specifications, implementation details and simulation results are discussed
First Measurements on the Timespot1 ASIC: a Fast-Timing, High-Rate Pixel-Matrix Front-End
No full texthis work presents the first measurements performed on the timespotQ asicN as the second
prototype developed for the timespot projectL the asic features a 32 × 32 channels hybridMpixel
matrixN targeted to spaceMtime tracking applications in high energy physics experimentsL the system
aims to achieve a time resolution of 30 ps or better at a maximum event rate of 3 MHz/channel
with a data driven interfaceN power consumption can be programmed to range between 1.2 W/cm2
and 2.6 W/cm2N the presented results include a description of the asic operation and a first
characterization of its performance in terms of time resolution
Sensore integrato di radiazione ionizzante e di particelle ionizzanti
No full textThis disclosure relates to a device for sensing radiation and/or ionizing particles. In particular, this disclosure relates to a completely depleted integrated semiconductor sensor having reverse biased PIN diodes which collect carriers generated by incident beams of radiation or of ionizing particles
A Configurable 64-Channel ASIC for Cherenkov Radiation Detection from Space
No full textThis work presents the development of a 64-channel application-specific integrated circuit (ASIC), implemented to detect the optical Cherenkov light from sub-orbital and orbital altitudes. These kinds of signals are generated by ultra-high energy cosmic rays (UHECRs) and cosmic neutrinos (CNs). The purpose of this front-end electronics is to provide a readout unit for a matrix of silicon photo-multipliers (SiPMs) to identify extensive air showers (EASs). Each event can be stored into a configurable array of 256 cells where the on-board digitization can take place with a programmable 12-bits Wilkinson analog-to-digital converter (ADC). The sampling, the conversion process, and the main digital logic of the ASIC run at 200 MHz, while the readout is managed by dedicated serializers operating at 400 MHz in double data rate (DDR). The chip is designed in a commercial 65 nm CMOS technology, ensuring a high configurability by selecting the partition of the channels, the resolution in the interval 8–12 bits, and the source of its trigger. The production and testing of the ASIC is planned for the forthcoming months
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