1,722,176 research outputs found
Neural Nets on FPGA a Machine Vision Algorithm Applied On MNIST Dataset Using Hls4ml Library
No full textIn this paper we describe a machine vision Neural Net al.gorithm implemented in a FPGA. The algorithm is trained on a hand written digit MNIST dataset. For Neural Net Intellectual Property generation it is used the hls4ml library, which is a really powerful tool for fast implementation of Neural Net on FPGA
Hough Transform Proposal and Simulations for Particle Track Recognition for LHC Phase-II Upgrade
Full text linkIn the near future, LHC experiments will continue future upgrades by overcoming the technological obsolescence of the detectors and the readout capabilities. Therefore, after the conclusion of a data collection period, CERN will have to face a long shutdown to improve overall performance, by updating the experiments, and implementing more advanced technologies and infrastructures. In particular, the largest LHC experiment, i.e., ATLAS, will upgrade parts of the detector, the trigger, and the data acquisition system. In addition, the ATLAS experiment will complete the implementation of new strategies, algorithms for data handling, and transmission to the final storage apparatus. This paper presents an overview of an upgrade planned for the second half of this decade for the ATLAS experiment. In particular, we show a study of a novel pattern recognition algorithm used in the trigger system, which is a device designed to provide the information needed to select physical events from unnecessary background data. The idea is to use a well known mathematical transform, the Hough transform, as the algorithm for the detection of particle trajectories. The effectiveness of the algorithm has already been validated in the past, regardless of particle physics applications, to recognize generic shapes within images. On the contrary, here, we first propose a software emulation tool, and a subsequent hardware implementation of the Hough transform, for particle physics applications. Until now, the Hough transform has never been implemented on electronics in particle physics experiments, and since a hardware implementation would provide benefits in terms of overall Latency, we complete the studies by comparing the simulated data with a physical system implemented on a Xilinx hardware accelerator (FELIX-II card). In more detail, we have implemented a low-abstraction RTL design of the Hough transform on Xilinx UltraScale+ FPGAs as target devices for filtering applications
Hough Transform FPGA solution for High Energy Physics online fast tracking
Full text linkIn the coming years, significant upgrades are planned for ATLAS and other High Energy
Physics experiments at CERN. Both the technologies and methodologies employed will undergo changes for the scheduled runs at the end of the decade. The LHC accelerator itself will also undergo multiple modifications, allowing it to achieve a peak of instantaneous luminosity up to 5–7.5 × 1034 cm−2 s−1. These enhancements will necessitate the experiments to handle a greater number of events at the conclusion of the data acquisition chain. For instance, ATLAS will be compelled to employ online tracking for its inner detector, aiming to achieve a final event rate of 10 kHz from the 1MHz originating from the Calorimeters and the Muon Spectrometer trigger discrimination.
Among the architectures explored to expedite fast tracking, there is consideration of a “hardware accelerator” farm, an infrastructure made of interconnected accelerators such as GPUs and FPGAs, designed to accelerate the tracking processes. The project presented here proposes a tuned Hough Transform algorithm implementation on high-end FPGA technology, specifically designed to adapt to various tracking situations. A development platform comprising software and firmware tools has been created to study different datasets. This platform utilizes software to simulate the firmware and to perform hardware tests. AMD-Xilinx FPGAs were chosen to implement and asses the system, with specific boards such as the VC709, the VCU1525 and the Alveo U250. Strategies such as low-level design for the firmware architecture, leveraging the card’s features like PCI Express data transfer, and the > 1 million gates array available have been exploited. The system underwent testing using internally simulated events generated within the ATLAS environment. Simulated 200 pile up events were used to evaluate the algorithm effectiveness. The average processing time was estimated to be below 5 μs, with the capability to concurrently process two events per algorithm instance. Internal efficiency tests have shown conditions where track finding performance for single muon tracking exceeded 95%
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Hardware implementation study of particle tracking algorithm on fpgas
Full text linkIn recent years, the technological node used to implement FPGA devices has led to very high performance in terms of computational capacity and in some applications these can be much more efficient than CPUs or other programmable devices. The clock managers and the enormous versatility of communication technology through digital transceivers place FPGAs in a prime position for many applications. For example, from real-time medical image analysis to high energy physics particle trajectory recognition, where computation time can be crucial, the benefits of using frontier FPGA capabilities are even more relevant. This paper shows an example of FPGA hardware implementation, via a firmware design, of a complex analytical algorithm: The Hough transform. This is a mathematical spatial transformation used here to facilitate on-the-fly recognition of the trajectories of ionising particles as they pass through the so-called tracker apparatus within high-energy physics detectors. This is a general study to demonstrate that this technique is not only implementable via software-based systems, but can also be exploited using consumer hardware devices. In this context the latter are known as hardware accelerators. In this article in particular, the Xilinx UltraScale+ FPGA is investigated as it belongs to one of the frontier family devices on the market. These FPGAs make it possible to reach high-speed clock frequencies at the expense of acceptable energy consumption thanks to the 14 nm technological node used by the vendor. These devices feature a huge number of gates, high-bandwidth memories, transceivers and other high-performance electronics in a single chip, enabling the design of large, complex and scalable architectures. In particular the Xilinx Alveo U250 has been investigated. A target frequency of 250 MHz and a total latency of 30 clock periods have been achieved using only the 17 ÷ 53% of LUTs, the 8 ÷ 12% of DSPs, the 1 ÷ 3% of Block Rams and a Flip Flop occupancy range of 9 ÷ 28%
Ricostruzione della volumetria ossea crestale mediante innesto di particolato cortico-midollare: caso clinico
No full textA high throughput Intrusion Detection System (IDS) to enhance the security of data transmission among research centers
Full text linkData breaches and cyberattacks represent severe problem in higher education institutions and universities that can result in illegal access to sensitive information and data loss. To enhance the security of data transmission, Intrusion Prevention Systems (IPS, i.e., firewalls) and Intrusion Detection Systems (IDS, i.e., packet sniffers) are used to detect potential threats in the exchanged data. IPSs and IDSs are usually designed as software programs running on a server machine.
However, when the speed of exchanged data is too high, this solution can become unreliable. In this case, IPSs and IDSs designed on a real hardware platform, such as ASICs and FPGAs, represent a more reliable solution. This paper presents a packet sniffer that was designed using a commercial FPGA development board. The system can support a data throughput of 10 Gbit/s with preliminary results showing that the speed of data transmission can be reliably extended to 100 Gbit/s. The designed system is highly configurable by the user and can enhance the data protection of information transmitted using the Ethernet protocol. It is particularly suited for the security of universities and research centers, where point-to-point network connections are dominant and large amount of sensitive data are shared among different hosts
- …
