1,296,361 research outputs found
Scan architecture with mutually exclusive scan segment activation for shift and capture power reduction
No full textPower dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. While several approaches have been recently proposed for reducing power dissipation during the shift cycle (minimum transition don't care fill, special scan cells and scan chain partitioning), very little work has been carried out towards reducing the peak power during test response capture and the few existing approaches for reducing capture power rely on complex ATPG algorithms. This paper proposes a scan architecture with mutually exclusive scan segment activation which overcomes the shortcomings of previous approaches. The proposed architecture achieves both shift and capture power reduction with no impact on the performance of the design, and with minimal impact on area and testing time (typically 2-3%). An algorithmic procedure for assigning flip-flips to scan segments enables reuse of test patterns generated by standard ATPG tools. An implementation of the proposed method had been integrated into an automated design flow using commercial synthesis and simulation tools which was used on a wide range of benchmark designs. Reductions up to 57% in average power, and up to 44% and 34% in peak power dissipation during shift and capture cycles, respectively, were obtained when using two scan segments. Increasing the number of scan segments to six leads to reductions of 96% and 80% in average power and respectively maximum number of simultaneous transitions
Numerically efficient modeling of CNT transistors with ballistic and non-ballistic effects for circuit simulation
No full textThis paper presents an efficient carbon nanotube (CNT) transistor modeling technique which is based on cubic spline approximation of the non-equilibrium mobile charge density. The approximation facilitates the solution of the selfconsistent voltage equation in a carbon nanotube so that calculation of the CNT drain-source current is accelerated by at least two orders of magnitude. A salient feature of the proposed technique is its ability to incorporate both ballistic and nonballistic transport effects without a significant computational cost. The proposed models have been extensively validated against reported CNT ballistic and non-ballistic transport theories and experimental results
Diagnosis of Multiple-Voltage Design with Bridge Defect
No full textMultiple voltage is an effective dynamic power reduction design technique commonly used in low-power ICs. To the best of our knowledge, there is no reported work for diagnosing multiple-voltage enabled ICs, and the aim of this paper is to propose a method for diagnosing bridge defects in such ICs. By using synthesized ISCAS benchmarks, with realistic extracted bridges and a parametric fault model, this paper investigates the impact of varying supply voltage on the accuracy of diagnosis and demonstrates how the additional voltage settings can be leveraged to improve the diagnosis resolution through a novel multivoltage diagnosis algorithm. In addition, it also identifies the most useful voltage settings to reduce diagnosis cost by eliminating tests at certain voltage setting using the proposed multivoltage diagnosis approach, thereby achieving high diagnosis accuracy at reduced cost
A Fast and Accurate Process Variation-aware Modeling Technique for Resistive Bridge Defects
No full textRecent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present there is no efficient device-level modeling technique that models the effect of process variation on resistive bridge defects. This paper presents a fast and accurate technique to achieve this, including modeling the effect of voltage and temperature variation using BSIM4 transistor model. To speedup the computation time and without compromising simulation accuracy (achieved through BSIM4) two efficient voltage approximation algorithms are proposed for calculating logic threshold of driven gates and voltages on bridged lines of a fault-site to calculate bridge critical resistance. Experiments are conducted on a 65-nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 53 times faster and in the worst case, error in bridge critical resistance is 2.64% when compared with HSPICE
Low power test compatibility classes: exploiting regularity for simultaneous reduction in test application time and power dissipation
No full textTraditional DFT methodologies increase useless power dissipation during testing and are not suitable for testing low power VLSI circuits leading to lower reliability and manufacturing yield. Traditional test scheduling approaches based on fixed test resource allocation decrease power dissipation at the expense of higher test application time. On the one hand it was shown that power conscious test synthesis and scheduling eliminate useless power dissipation. On the other hand by exploiting regularity in BIST RTL data paths using test compatibility classes an improvement in test application time, BIST area overhead, performance degradation, volume of test data, and fault escape probability is achieved. This paper shows that when combining power conscious test synthesis and scheduling with the test compatibility classes into low power test compatibility classes, simultaneous reduction in test application time and power dissipation is obtained
Low-energy standby-sparing for hard real-time systems
No full textTime-redundancy techniques are commonly used in real-time systems to achieve fault tolerance without incurring high energy overhead. However, reliability requirements of hard real-time systems that are used in safety-critical applications are so stringent that time-redundancy techniques are sometimes unable to achieve them. Standby sparing as a hardware redundancy technique can be used to meet high reliability requirements of safety-critical applications. However, conventional standby-sparing techniques are not suitable for low-energy hard real-time systems as they either impose considerable energy overheads or are not proper for hard timing constraints. In this paper we provide a technique to use standby sparing for hard real-time systems with limited energy budgets. The principal contribution of this work is an online energy management technique which is specifically developed for standby-sparing systems that are used in hard real-time applications. This technique operates at runtime and exploits dynamic slacks to reduce the energy consumption while guaranteeing hard deadlines. We compared the low-energy standby-sparing (LESS) system with a low-energy time redundancy system (from a previous work). The results show that for relaxed time constraints, the LESS system is more reliable and provides about 26% energy saving as compared to the time-redundancy system. For tight deadlines when the time redundancy system is not sufficiently reliable (for safety-critical application), the LESS system preserves its reliability but with about 49% more energy consumptio
Asynchronous Transient Resilient Links for NoC
No full textThis paper proposes a new link for asynchronous NoC communications that is resilient to transient faults on the wires of the link without impact on the data transfer capability. Resilience to transients is achieved by exploiting the phase relationship between data symbols and a common reference symbol where the symbols are transmitted using additional wires. Detection of transient faults is performed by comparison of the data symbol and the reference symbol. We demonstrate it is possible to achieve a similar number of transitions per bit as existing delay insensitive codes, from a power consumption point of view, but achieving resilience to transient faults. The link has been synthesized and validated using 0.12 ?m technology and power, area and performance are given. It has been shown that the link area cost is 409 ?m2 per data bit and energy per bit is 356 fJ/bit. Latency through the link is 0.8 ns and the maximum operating frequency or throughput of the link is 1.056 GHz
Bridging fault test method with adaptive power management awareness
No full textA key design constraint of circuits used in handheld devices is the power consumption, mainly due to battery life limitations. Adaptive power management (APM) techniques aim to increase the battery life of such devices by adjusting the supply voltage and operating frequency, and thus the power consumption, according to the workload. Testing for resistive bridging defects in APM-enabled designs raises a number of challenges due to their complex analog behavior. Testing at more than one supply voltage setting can be employed to improve defect coverage in such systems, however, switching between several supply voltage settings has a detrimental impact on the overall cost of test. This paper proposes a multi-Vdd automatic test generation method which delivers 100% resistive bridging defect coverage and also a way of reducing the number of supply voltage settings required during test through test point insertion. The proposed techniques have been experimentally validated using a number of benchmark circuits
'Switched-Current Wave Group Delay Equalizers'
No full textTo improve the elliptic filters step response, group delay equalizers are often cascaded with the filters. This paper describes the design of switched-current (SI) group delay equalizer using wave synthesis technique. This design is based on a new all-pass circuit, where the poles are generated using wave structures. Simulation results are included demonstrating that the 3rd-order SI group delay equalizer can reduces the amount of overshoot in 100kHz elliptic low-pass filter step response by 50%. This is as a result of reducing the filter group delay variation from 2.29us to 0.32us when the group delay equalizer is employe
Combined Time and Information Redundancy for SEU-Tolerance in Energy-Efficient Real-Time Systems
No full textRecently the trade-off between energy consumption and fault-tolerance in real-time systems has been highlighted. These works have focused on dynamic voltage scaling (DVS) to reduce dynamic energy dissipation and on time redundancy to achieve transient-fault tolerance. While the time redundancy technique exploits the available slack time to increase the fault-tolerance by performing recovery executions, DVS exploits slack time to save energy. Therefore we believe there is a resource conflict between the time-redundancy technique and DVS. The first aim of this paper is to propose the usage of information redundancy to solve this problem. We demonstrate through analytical and experimental studies that it is possible to achieve both higher transient fault-tolerance (tolerance to single event upsets (SEU)) and less energy using a combination of information and time redundancy when compared with using time redundancy alone. The second aim of this paper is to analyze the interplay of transient-fault tolerance (SEU-tolerance) and adaptive body biasing (ABB) used to reduce static leakage energy, which has not been addressed in previous studies. We show that the same technique (i.e. the combination of time and information redundancy) is applicable to ABB-enabled systems and provides more advantages than time redundancy alone
- …
