1,721,001 research outputs found
FELIX: developing a new detector interface for ATLAS trigger and readout
No full textStarting during the upcoming major LHC shutdown (2019-2021), the ATLAS experiment at CERN will move to the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX will function as a router between custom serial links and a commodity switch network, which will use industry standard technologies to communicate with data collection and processing components. This note will describe the FELIX system design as well as report on results of the ongoing development program
The ATLAS FELIX Project
No full textFELIX is a key component of the new readout architecture for the ATLAS experiment at CERN. It consists of commodity servers hosting PCIe cards, which receive data from detector and trigger electronics over optical links and transfer them to the host system via Direct Memory Access (DMA). From there, a software routing platform serves data to subscribed network peers, as well as routing commands to detector and trigger electronics in the other direction. While in the ATLAS context FELIX is designed to integrate with the ATLAS TDAQ software infrastructure, it has also been used in numerous other experiments and is designed to be flexible.
The FELIX codebase comprises both firmware (gateware) and software components, and is designed and maintained by researchers at institutes who are members of the ATLAS Collaboration.
The codebase is available in open-source form for both firmware and software
FELIX and the SW ROD
No full textAfter the current LHC shutdown (2019-2022), the ATLAS experiment will be required to operate in an increasingly harsh collision environment. To maintain physics performance, the ATLAS experiment is undergoing a series of upgrades. A key goal of this upgrade is to improve the capacity and flexibility of the detector readout system. To this end, the Front-End Link eXchange (FELIX) system has been developed. FELIX acts as the interface between the data acquisition; detector control and TTC (Timing, Trigger and Control) systems; and new or updated trigger and detector front-end electronics. The system functions as a router between custom serial links from front end ASICs and FPGAs to data collection and processing components via a commodity switched network. The serial links may aggregate many slower links or be a single high bandwidth link. FELIX also forwards the LHC bunch-crossing clock, fixed latency trigger accepts and resets received from the TTC system to front-end electronics. FELIX uses commodity server technology in combination with FPGA-based PCIe I/O cards. FELIX servers run a software routing platform serving data to network clients. Commodity servers connected to FELIX systems via the same network run the new multi-threaded Software Readout Driver (SW ROD) infrastructure for event fragment building, buffering and detector-specific processing to facilitate online selection. This presentation will cover the design of FELIX and the SW ROD, as well as the results of the installation and commissioning activities for the full system in spring 2021
Performance of the ATLAS tau-lepton trigger at the LHC in Run 2.
No full textThe ATLAS experiment has a rich physics program of Standard Model measurements and searches for physics Beyond the Standard Model involving tau leptons. Most of these analyses depend on an efficient tau-lepton trigger that can cope with the overwhelming background from multi-jet events produced in proton-proton collisions at the Large Hadron Collider. The ATLAS trigger system is composed of two stages. At Level-1, tau leptons are reconstructed as energy deposits in neighbouring towers of calorimeter cells. The High Level Trigger (HLT) exploits the full calorimeter granularity as well as inner-detector tracks, and runs reconstruction and identification algorithms similar to those used in the offline reconstruction. The performance of the tau-lepton trigger in ATLAS Run-2 data will be discussed, and trigger efficiencies measured with a tag-and-probe method will be presented. An emphasis will be made on the improved HLT algorithms deployed in 2018 and mentioned below. The association of tracks to the energy deposit in the calorimeter was tightened to reduce the contamination from fake tracks at high pileup. An energy calibration based on a Boosted Regression Tree with improved energy resolution has replaced the simpler calibration based on pileup subtraction and calorimeter response correction. An identification algorithm based on a Recurrent Neural Network was also deployed, which provides increased jet rejection compared to the previously-used Boosted Decision Tree identification algorithm
FELIX: the new detector readout system for the ATLAS experiment
No full textStarting during the upcoming major LHC shutdown from 2019-2021, the ATLAS experiment at CERN will move to the the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX will function as a router between custom serial links and a commodity switch network, which will use industry standard technologies to communicate with data collection and processing components. The FELIX system is being developed using commercial-off-the-shelf server PC technology in combination with a FPGA-based PCIe Gen3 I/O card hosting GigaBit Transceiver links and with Timing, Trigger and Control connectivity provided by an FMC-based mezzanine card. FELIX functions will be implemented with dedicated firmware for the Xilinx FPGA (Virtex 7 and Kintex UltraScale) installed on the I/O card alongside an interrupt-driven Linux kernel driver and user-space software. On the network side, FELIX is able to connect to both Ethernet or Infiniband network architectures. This presentation will describe the FELIX system design as well as reporting on results of the ongoing development program
FELIX: developing a new detector interface for ATLAS trigger and readout
No full textStarting during the upcoming major LHC shutdown (2019-2021), the ATLAS experiment at CERN will move to the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX will function as a router between custom serial links and a commodity switch network, which will use industry standard technologies to communicate with data collection and processing components. This presentation will describe the FELIX system design as well as report on results of the ongoing development program
FELIX: the Detector Interface for the ATLAS Experiment at CERN
No full textThe Front-End Link eXchange (FELIX) system is an interface between the trigger and detector electronics and commodity switched networks for the ATLAS experiment at CERN. In preparation for the LHC Run 3, to start in 2022, the system is being installed to read out the new electromagnetic calorimeter, calorimeter trigger, and muon components being installed as part of the ongoing ATLAS upgrade programme. The detector and trigger electronic systems are largely custom and fully synchronous with respect to the 40.08 MHz clock of the Large Hadron Collider (LHC). The FELIX system uses FPGAs on server-hosted PCIe boards to pass data between custom data links connected to the detector and trigger electronics and host system memory over a PCIe interface then route data to network clients, such as the Software Readout Drivers (SW ROD), via a dedicated software platform running on these machines. The SW RODs build event fragments, buffer data, perform detector-specific processing and provide data for the ATLAS High Level Trigger. The FELIX approach takes advantage of modern FPGAs and commodity computing to reduce the system complexity and effort needed to support data acquisition systems in comparison to previous designs. Future upgrades of the experiment will introduce FELIX to read out all other detector components
Track reconstruction for the ATLAS Phase-II Event Filter using GNNs on FPGAs
No full textThe High-Luminosity LHC (HL-LHC) will provide an order of magnitude increase in integrated luminosity and enhance the discovery reach for new phenomena. The increased pile-up necessitates major upgrades to the ATLAS detector and trigger. The Phase-II trigger will consist of two levels, a hardware-based Level-0 trigger and an Event Filter (EF) with tracking capabilities. Within the Trigger and Data Acquisition group, a heterogeneous computing farm consisting of CPUs and potentially GPUs and/or FPGAs is under study, together with the use of modern machine learning algorithms such as Graph Neural Networks (GNNs). GNNs are a powerful class of geometric deep learning methods for modelling spatial dependencies via message passing over graphs. They are well-suited for track reconstruction tasks by learning on an expressive structured graph representation of hit data and considerable speedup over CPU-based execution is possible on FPGAs. The focus of this publication is a study of track reconstruction for the Phase-II EF system using GNNs on FPGAs. We explore each of the steps in a GNN-based EF tracking pipeline: graph construction, edge classification using an interaction network, and track reconstruction. Several methods and hardware platforms are under evaluation, studying resource utilisation and minimization of model size using quantization aware training, while simultaneously retaining high track reconstruction efficiency and low fake rates required for the EF tracking system
The new Muon-to-Central-Trigger-Processor Interface at ATLAS
No full textThe ATLAS trigger system includes a Level-1 (L1) trigger based on custom electronics and firmware, and a high-level trigger based on off-the-shelf hardware and processing software. The L1 trigger system uses information from the calorimeters and from the muon trigger detectors, consisting of Resistive Plate Chambers in the barrel, and of Thin-Gap Chambers, small-strip Thin-Gap Chambers and MicroMegas in the endcaps. Once information from all muon trigger sectors has been received, trigger candidate multiplicities are calculated by the Muon-to-Central-Trigger-Processor Interface (MUCTPI). In the next stage, muon multiplicity information is sent to the Central-Trigger-Processor (CTP) and trigger objects are sent to the topological trigger. The CTP combines the information received from the MUCTPI with the trigger information from the calorimeters and the topological trigger, and takes the L1 trigger decision. As part of the upgrade of the ATLAS L1 trigger system for Run-3 of the Large Hadron Collider (LHC), a new MUCTPI has been designed and commissioned. The upgrade includes a replacement of 18 VME boards by a single ATCA board based on three high-end FPGAs and one System-on-Chip (SoC), with the sector-logic input data received on 208 optical links. Two FPGAs are used as Muon Sector Processors (MSPs), one MSP for each side of the ATLAS detector, and one FPGA used as Trigger and Readout Processor (TRP). The MSPs receive trigger information from the 208 muon trigger sectors, conduct overlap handling to flag/remove duplicate muon candidates, calculate the transverse momentum threshold multiplicities and send trigger objects to the topological trigger system. The TRP combines the trigger information, and sends trigger multiplicities to the CTP and trigger data to the Data Acquisition (DAQ) system. The DAQ Run-Control software for configuration, control and monitoring of the MUCTPI runs directly on the SoC. We discuss the commissioning and integration of the new MUCTPI used in ATLAS from the beginning of Run-3. In particular, we describe monitoring tools which have been developed for the commissioning and operation of the new MUCTPI, and challenges which had to be overcome to integrate the system in the experiment. Furthermore, we report the performance of the MUCTPI at the beginning of Run-3 of the LHC
Leveraging the Run 3 experience for the evolution of the ATLAS software-based readout towards HL-LHC
No full textThe High-Luminosity Large Hadron Collider (HL-LHC), scheduled to start operating in 2029, aims to increase the instantaneous luminosity by a factor of 10 compared to the LHC. To match this increase, the ATLAS experiment has been implementing a major upgrade program divided into two phases. The first phase (Phase-I), completed in 2022, introduced new trigger and detector systems that have been used during the Run 3 data taking period which began in July 2022. These systems have been used in conjunction with the new Data Acquisition (DAQ) Readout system, based on a software application called Software Readout Driver (SW~ROD). SW~ROD receives and aggregates data from the front-end electronics via the Front-End Link eXchange (FELIX) system and passes aggregated data fragments to the High-Level Trigger (HLT) system. During Run 3, SW~ROD operates in parallel with the legacy Readout System (ROS) at an input rate of 100 kHz. For the Phase-II, the legacy ROS will be completely replaced with a new system based on the next generation of FELIX and an evolution of the SW~ROD application called Data Handler. Data Handler has the same functional requirements as SW~ROD but must be able to operate at an input rate of 1 MHz. To facilitate this evolution the SW~ROD has been implemented using plugin architecture. This contribution presents the design and implementation of the SW~ROD application for Run 3, along with the strategy for its evolution to the Phase-II Readout system. It discusses the lessons learned during Run~3 and describes the challenges that have been addressed to accomplish the demanding performance requirements of HL-LHC
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