61 research outputs found
RD53 Collaboration and CHIPIX65 Project for the development of an innovative Pixel Front End Chip for HL-LHC
Full text linkNew development on digital architecture for efficient pixel readout ASIC at extreme hit rate for hep detectors at HL-LHC
No full textA novel region-based pixel digital architecture for latency buffering and trigger matching able to withstand extended trigger latencies and unprecedented data rates at the High-Luminosity LHC upgrade is presented. The architecture features above 99.5% efficiency at nominal 3 GHz/cm 2 pixel hit rate and 1 MHz trigger rate with 12.5 μs trigger latency foreseen at HL-LHC. The overall inefficiency is dominated by dead-time in analogue front-end channels. The digital architecture is organized in pixel regions composed of 4×4 pixels. Charge information is retrieved from each pixel by means of Time-over-Threshold (ToT) using 5-bit counters. A common digital logic shared among pixels stores hits information for the whole trigger latency, handles the local configuration, performs trigger matching and sends zero-suppressed hit data to the chip periphery upon a trigger request. Data compression based on priority queues has been introduced in order to save area and power in the pixel region. The logic has been implemented in a commercial 65 nm CMOS pixel ASIC demonstrator prototyped as part of the Italian INFN CHIPIX65 project. Design specifications, implementation details and simulation results are discussed
RD53 Collaboration and CHIPIX65 Project for the development of an innovative Pixel Front End Chip for HL-LHC
Full text linkPixel detectors at HL-LHC experiments will be exposed to unprecedented level of radiation and particle flux. This paper describes the program of development of an innovative pixel chip using a CMOS 65nm technology for the first time in HEP community, for experiments with extreme particle rates and radiation at future High Energy Physics colliders. The RD53 collaboration effort is described together with the CHIPIX65 INFN project
A Pixel Read-Out Front-End in 28 nm CMOS with Time and Space Resolution
Full text linkFuture high luminosity colliders will require front-end electronics with unprecedented performance, both in space and time resolution (tens of micrometers and tens of picoseconds) and in radiation hardness (tens of megagray). Moreover, the high number of events will generate an enormous quantity of data (some terabits per second), and the limited bandwidth requires to perform data selection as close as possible to the front-end stage, to reduce the amount of data transmitted and stored for off-line analysis.The TimeSpOT (TIME and SPace real-time Operating Tracker) project, funded by INFN, is developing a complete demonstrator of a tracking device including all the features needed for future high luminosity experiments.In this presentation, we describe the first prototype of the readout electronics in 28 nm CMOS technology. The modules of the front-end circuitry have been designed and integrated in a test chip, which will allow us to characterize each block separately, and to connect them in a processing chain to evaluate the overall performance
Preliminary timing measurements on a data acquisition chain for a SiPM-based detector for prostate imaging
No full textProstate cancer (PC) is one of the most common diseases in western countries and a leading cause of cancer death. A variety of treatment options are available but a precise disease characterization is needed: evaluation of cancer location, size, and extent and an indication of tumor aggressiveness. The current standard for diagnosing PC is transrectal ultrasound guided sextant biopsy. A novel multidisciplinary approach is required. Imaging may play a key role provided that dedicated prostate imagers and procedures are available: considerable improvements have been achieved in diagnosis with the Magnetic Resonance Imaging (MRI) and nuclear medicine (Positron Emission Tomography (PET) and Single Photon Emission Computed Tomography (SPECT)) techniques. Nevertheless, due to sub-optimal prostate imaging geometries with these generic large instruments preventing separation of the signal from surrounding organs, the sensitivity, spatial resolution and lesion contrast detected are lower compared to what can be potentially achievable with optimized dedicated prostate imagers and procedures. Fully exploiting the Time Of Flight (TOF) capability would allow not only to increase the Signal-to-Noise ratio (SNR) / Noise Equivalent Count Rate (NECR) but also to get rid of the huge background coming from neighboring organs i.e. the bladder. Recently a new research project was initiated by a large INFN collaboration, and a "TOF-PET and MRI for prostate cancer diagnosis and follow up experiment" (TOPEM) was financed as a 3-year experiment by the Italian "INFN Commissione Scientifica Nazionale V" with the goal of designing, building and testing in phantom tests an endorectal PET-TOF probe compatible with MRI. © 2011 Elsevier B.V
Results from CHIPIX-FE0, a small-scale prototype of a new generation pixel readout ASIC in 65 nm CMOS for HL-LHC
Full text linkA prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 x 64 pixels with 50 m x 50 m pixel size embedding two different architectures of analog front-ends working in parallel. The final layout of the chip was submitted and accepted for fabrication on July 2016. Chips were received back from the foundry on October 2016 and successfully characterized before irradiation. Several irradiation campaigns with X-rays have been accomplished during 2017 at Padova INFN and CERN EP/ESE facilities under different uniformity and temperature conditions up to 630 Mrad Total Ionizing Dose (TID). These studies corfirmed negligible degradation of analog front-ends performance after irradiation. First sample chips have been also bump-bonded to 50 m x 50 m and 25 m x 100 m 3D sensors provided by Trento FBK. This represented a major milestone for the entire CHIPIX65 project, offering to the pixel community the first example of a complete readout chip in 65 nm CMOS technology coupled to such a kind of silicon detectors. Extensive characterizations with laser and radioactive sources have started.This paper briefly summarizes most important pre- and post-irradiation results, along with preliminary results obtained from chips bump-bonded to 3D sensors. Selected components of the CHIPIX65 demonstrator have been finally integrated into the large-scale RD53A prototype submitted at the end of summer 2017 by the CERN RD53 international collaboration on 65 nm CMOS technology
Design and testing of CMOS radiation detectors for High Energy Physics Experiments
Full text linkIn recent years, the study and the development of novel architectures and tech-
nologies to improve performance of silicon pixel detectors became a pivotal node
for High Energy Physics (HEP) experiments. Their extremely tight constraints of
spatial resolution, low power dissipation, speed, granularity, signal-to-noise ratio
and radiation hardness, led the scientific community to continuously research new
solutions to satisfy newer and more stringent requirements. In this context, the two
main categories of detectors technologies have been represented by Hybrid Pixel
Detectors (HPDs) and Monolithic Active Pixel Sensors (MAPS).
Traditionally, HPDs constitute the more widespread technology for particle pixel
detectors: due to their excellent characteristics, they are adopted for the inner layers
of the most of current main HEP experiments. However, on the other side, the
relatively novel monolithic sensors technology became recently more and more
interesting as leading replacing technology due to its improved radiation hardness
and the lower material budget and cost with respect to HPDs.
In this thesis an introduction to these technologies will be carried out and some
related research results will be shown.
In Chapter 1 Hybrid Pixel Detectors technology will be described, with an
additional part dedicated to some literature examples about HEP experiments which
adopted this kind of sensors for their inner layers. This chapter acts as an introduction
to the CHIPIX65 (CHIp for PIXel detector in a 65 nm process) prototype shown in
Chapter 3 and to the Phase-Locked Loop described in Chapter 5.In Chapter 2 MAPS (Monolithic Active Pixel Sensors) technology will be intro-
duced, from the early prototypes based on 3-T and 4-T architecture until the last
examples of monolithic sensors implemented inside more recent particle detectors
upgrades. This part is preparatory to Chapter 5, where the MATISSE prototype is
described both to the development and to the testing point of view.
Chapter 3 is dedicated to CHIPIX65 project and the development of a novel
prototype of an 65 nm CMOS HPD: realized in collaboration of some INFN Italian
groups, this is the first example of HPD fully developed in a sub-micron CMOS
technology. Starting with a short introduction to architecture and readout modes,
this chapter shows some important testing results presented in Strasbourg during an
IEEE MIC-NSS Conference talk in 2016.
Chapter 4 is fully dedicated to a low-noise and compact Phase-Locked Loop
(PLL) built in the same 65 nm CMOS technology. After some theoretical and
introductory sections, the prototype will be described and test results provided.
Chapter 5 is fully dedicated to the development and test of a prototype of MAPS,
called MATISSE (Monolithic AcTIve pixel SenSor Electronics). Developed by
INFN groups of Turin and Padua, University of Trento and TIFPA, it is an example of
a fully-depleted monolithic active sensor. Here, some sensor and readout electronics
will be described, followed by some tests. These results have been presented during
a poster session in Atlanta during the IEEE MIC-NSS Conference in 2017.
Appendices will cover some follow-up topics related to the previous sections.
Appendix A summarizes radiation effects on silicon devices, both total dose and
heavy-ions effect: this section is useful to referring to all the parts related to radiation
hardness tests of described prototypes.
Appendix B outlines some practical guidelines about Process Design Kit (PDK)
of a given technology process. Indeed, before starting the design of any ASIC device,
a PDK needs to be provided by the foundry, installed and configured in order to
allow to work with.
Appendix C is dedicated to some theoretical issues on oscillator phase noise,
which represent a huge subject in Phase-Lock Loop theory; however, since it is not
covered by the analysis and tests on the PLL prototype, it has been chosen to put this
part separately to Chapter 4
CHIPIX65: Developments on a new generation pixel readout ASIC in CMOS 65 nm for HEP experiments
No full textPixel detectors at HL-LHC experiments or other future experiments are facing new challenges, especially in terms of unprecedented levels of radiation and particle flux. This paper describes the progress made by the CHIPIX65 project of INFN for the development of a new generation readout ASIC using CMOS 65 nm technology
First Measurements of a Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for Extreme Rate HEP Detectors at HL-LHC
Full text linkA first prototype of a readout ASIC in CMOS 65nm for a pixel detector at High Luminosity LHC is described. The pixel cell area is 50x50 um2 and the matrix consists of 64x64 pixels. The chip was designed to guarantee high efficiency at extreme data rates for very low signals and with low power consumption. Two different analogue front-end designs, one synchronous and one asynchronous, were implemented, both occupying an area of 35x35 um2. ENC value is below 100e- for an input capacitance of 50 fF and in-time threshold below 1000e-. Leakage current compensation up to 50 nA with power consumption below 5 uW. A ToT technique is used to perform charge digitization with 5-bit precision using either a 40 MHz clock or a local Fast Oscillator up to 800 MHz. Internal 10-bit DAC's are used for biasing, while monitoring is provided by a 12-bit ADC. A novel digital architecture has been developed to ensure above 99.5% hit efficiency at pixel hit rates up to 3 GHz/cm2, trigger rates up to 1 MHz and trigger latency of 12.5 us. The total power consumption per pixel is below 5uW. Analogue dead-time is below 1%. Data are sent via a serializer connected to a CMOS-to-SLVS transmitter working at 320 MHz. All IP-blocks and front-ends used are silicon-proven and tested after exposure to ionizing radiation levels of 500-800 Mrad. The chip was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 and was submitted in July 2016 for production. Early test results for both front-ends regarding minimum threshold, auto-zeroing and low-noise performance are high encouraging and will be presented in this paper
- …
