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학습 표현과 특징 풀링 연산의 활용을 통한 음성발화 감정 인식 향상에 관한 연구
No full text학위논문(박사) - 한국과학기술원 : 전산학부, 2025.2,[v, 71 p. :]Speech Emotion Recognition aims to enhance human-computer interaction by identifying emotional states conveyed through speech. Despite advancements in self-supervised learning (SSL) models, leveraging these models for emotionally expressive speech remains challenging due to domain mismatch between pre-training data and emotionally rich speech data, variability in speech signal lengths, and the unequal distribution of emotional cues across speech segments. This thesis proposes three novel approaches to address these challenges. First, it integrates SSL representations with domain-agnostic spectral features using the Mixture of Experts method, mitigating domain mismatch and complementarily leveraging the strengths of both representations. Second, Segmental Average Pooling is introduced to prioritize verbal segments over non-verbal segments, reducing the influence of irrelevant non-verbal content and addressing information dilution. Third, an attention-based Context-Aware Pooling is designed to dynamically weigh the emotional relevance of both verbal and non-verbal segments, effectively capturing nuanced emotional contexts. Extensive experiments on the IEMOCAP and KEMDy19 datasets demonstrate state-of-the-art performance with significant improvements over existing baselines, validating the effectiveness of these methods in resolving domain mism한국과학기술원 :전산학부
차세대 무선 통신을 위한 저잡음 저전력 서브 테라헤르츠 클락 생성기
No full text학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2025.2,[v, 55 p. :]Beyond-5G wireless communications have attracted attention for their ability to rapidly transmit large amounts of data within a short time due to their wide data bandwidth. To achieve such high transmission rates, higher carrier frequencies than those used in conventional communications are required, and clock generators having such ultra-low noise signals are essential. Compared with commonly used sub-sampling-based phase-locked loops (PLLs), fundamental-sampling-based PLLs have larger phase error detection gain at higher carrier frequencies, making them more advantageous for generating low-noise, high-frequency carrier signals. This dissertation proposed a low-noise, low-power sub-terahertz PLL based on a fundamental-sampling phase detector. To address the limited bandwidth issue of the PLL, a separate proportional path was introduced to quickly remove the noise of the oscillator, and a reset switch was introduced to enhance the stability of the loop. Furthermore, complementary fundamental-sampling phase detectors-based low-spur PLL was also proposed to reduce inherent spurs caused by the operation of the fundamental-sampling phase detector.한국과학기술원 :전기및전자공학부
단거리 칩 간의 통신을 위한 에너지 효율적인 누전잡음에 강인한 싱글-엔드형 PAM-4 송수신기
No full text학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2025.2,[vii, 93 p. :]With recent advancements in packaging technology, the use of short-reach channels in chip-to-chip communication has increased. This dissertation focuses on two key studies among various short-reach channel applications: 1) A study on transmitters in PCB-level chip-to-chip links for improving the energy efficiency of IoT devices, 2) A study on transceivers to address crosstalk caused by high-density channels in chiplet communication within 2.5D packaging. In the first study, a transmitter employing stepwise driving was proposed to minimize switching power in the output driver. At 200Mb/s, the proposed output driver achieved a power reduction of over 63% compared to the conventional driver that consumes power proportional to CV2. In the second study, circuit techniques to minimize crosstalk and adaptive methods to address performance degradation due to temperature variations were proposed. The proposed 12-Gb/s single-ended PAM-4 transceivers demonstrated effective crosstalk cancellation under temperature variations.한국과학기술원 :전기및전자공학부
짧은 영상 제공 플랫폼의 아동 집중력에 대한 영향
No full text학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2025.2,[v, 68 p. :]Short-form video platforms, which consist of many brief videos, are widely used today. However, the potential side effects, especially on children, remains unclear and has not been well explored. Given the frequent switching between different videos in short-form video platforms, prior work has described how frequently swiping through the videos can be considered a form of context switching and negatively affect cognition. In this thesis, we explore the impact of short-form video platforms on children’s cognition and in particular, two key components of short-form videos: the easy-to-use swipe-based user interface, and the personalized recommendation system that continuously suggests videos that might be of interest to users. A user study for children was carefully designed to isolate the impact of these two components and the digit span task was used to measure children's cognition. To provide a baseline comparison reference, a separate experimental group was created which was shown a long-form video that does not necessarily have the context switching effect. In addition, another long-form video group performed media multitasking, a known context switching activity. A between-subjects experiment with elementary students in years four through six (n = 180) was conducted and both forward and backward digit span task was used to measure working memory, attention, and executive function of the children. initial analysis of the user study demonstrated the effect of short-form video consumption had minimal impact on children’s cognition. Unexpectedly, the no-context-switching group occasionally exhibited lower scores, while the media multitasking group outperformed other groups. Furthermore, input interval analysis suggested that the swipe-based interface and recommendation system might exacerbate the cognitive effects of short-form videos on children.한국과학기술원 :전기및전자공학부
고속 링크를 위한 저지터 고주파 체배 지연 고정 루프 설계
No full text학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2025.2,[v, 61 p. :]With the surge in demand for massive data transmission, the need for high-frequency clock generators with high area efficiency and low noise performance has increased. Since the traditional phase-locked loops (PLLs) have a limited narrow bandwidth, they rely on LC-based voltage-controlled oscillators (VCOs) for their superior noise characteristics, leading to significant chip area consumption. In contrast, ring oscillators (RO) offer advantages in terms of area and frequency scalability, but their inherent noise performance limits their ability to achieve excellent jitter performance. Among RO-based clock generators, the multiplying delay-locked loop (MDLL) can achieve superior jitter performance. The MDLL periodically replaces the edges of the RO with clean reference edges to reset accumulated jitter, which allows for improved jitter performance. However, the MDLL faces limitations in high frequency operation due to the multiplexer (MUX), which poses challenges in generating selection pulses at high frequencies and introduces additional delay in the oscillation path.
In this dissertation, a low-noise, high-speed MDLL based on an RO with a power-gating (PG) technique is proposed. Instead of employing a conventional MUX, the PG technique is used to periodically turn the RO on and off at every reference clock, thereby resetting accumulated jitter and resolving the speed limitation due to the MUX. During the periods when the RO is off, a single pulse generator is used to fill in a missing pulse, and background calibration is applied to correct various timing errors. Additionally, to prevent performance degradation due to mismatches between multiple calibration loops, an output-edge selective divide-by-4 divider was designed to share a common calibration path. Furthermore, a hybrid accumulator was introduced to ensure an effective calibration of a frequency error of an RO. The proposed RO-based PG-MDLL was fabricated using a 40-nm CMOS process, occupying an area of 0.066 mm² and consuming 14.7 mW of power. It achieved an operating frequency of 12.24 GHz, with an integrated jitterRMS of 122 fs and a spur performance of −60 dBc.한국과학기술원 :전기및전자공학부
고집적 컴퓨팅 인 메모리 시스템을 위한 하프니아 강유전체 터널 정션 소자
No full text학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2025.2,[vii, [82] p. :]This dissertation focuses on the development of next-generation memory devices for artificial intelligence (AI) and computing-in-memory (CIM) applications. Specifically, it presents novel methodologies to enhance the performance and reliability of hafnium-based ferroelectric tunnel junctions (FTJs). To maintain high polarization and stability in ultra-thin hafnium zirconium oxide (HZO) ferroelectric films, a low-damage top electrode deposition process was introduced, minimizing defects and reducing leakage currents. This process significantly enhanced the remnant polarization and overall device reliability by decreasing oxygen vacancies and interfacial defects. Furthermore, by incorporating a thin indium oxide (In₂O₃) layer, an asymmetric distribution of oxygen vacancies was achieved, leading to a substantial increase in the tunneling electroresistance (TER) ratio. Oxygen vacancies in the In₂O₃ layer modulate the tunneling barrier height depending on the polarization direction, effectively controlling the current flow. As a result, a high-performance FTJ with a TER ratio exceeding 10⁵ was realized, greatly surpassing the performance of conventional hafnium-based FTJs. Additionally, a new capacitive ternary content-addressable memory (Cap-TCAM) architecture based on self-rectifying FTJs was proposed. This design eliminates the need for precharge operations and pass gates, thereby reducing energy consumption and circuit complexity. Experimental results demonstrated that the proposed Cap-TCAM reduces energy consumption by up to 80 times compared to traditional SRAM-based TCAMs, while also improving search speed and accuracy. These features are expected to provide high performance and energy efficiency in AI applications such as pattern recognition and network routing. This research marks a significant milestone in advancing hafnium-based ferroelectric devices and contributes meaningfully to the development of next-generation non-volatile memory technologies.한국과학기술원 :전기및전자공학부
디지털 집약적 연속시간 델타-시그마 모듈레이터 구조 설계
No full text학위논문(박사) - 한국과학기술원 : 전기및전자공학부, 2025.2,[iv, 52 p. :]This dissertation explores digital-intensive continuous-time (CT) delta-sigma modulator (DSM) architectures, a concept that is rarely studied compared to existing approaches. It focuses on employing SAR-assisted digital noise coupling (DNC), which shifts most analog processing to the digital domain. By processing residues digitally and leveraging the digital-friendly nature of the SAR quantizer, the DNC architecture fully benefits from technology scaling, as well as from improved area and power efficiency, robustness, and flexibility. The first part of this work addresses the unwanted quantization noise inherent in the DNC architecture through the hybrid noise coupling technique. Fabricated in a 28-nm CMOS process, the prototype demonstrates a 5-dB improvement in SNDR compared to DNC-only implementations, without introducing significant hardware complexity. It consumes 0.22 mW at a 1.8-V supply, achieving an SNDR of 95.8 dB and a DR of 101.8 dB at a bandwidth of 15.625 kHz. To further enhance power efficiency, a digital adder-free 3rd-order DNC filter, combined with a digital back-end integrator, is proposed. This innovation enables a single-opamp, digital-intensive, 4th-order CT DSM to achieve 3rd-order noise shaping using only delay cells, representing the highest noise-coupling filter order implemented to date. Fabricated in a 28-nm CMOS process, this design demonstrates state-of-the-art performance and robustness across multiple samples, process corners, and power supply variations, with only a 0.5-dB SNDR deviation under all conditions. As a result, this work achieves one of the best energy efficiencies among state-of-the-art DSMs in a 200-kHz bandwidth, featuring the highest Schreier Figure of Merit (FoM) of 179.2 dB and the lowest Walden FoM of 37.7 fJ/conv. step, while consuming only 0.31 mW at a 1-V supply. These results imply that the proposed architecture can be a strong candidate for advanced technology nodes with reduced supply voltages.한국과학기술원 :전기및전자공학부