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A Neuromodulation-based Spiking Neural Network using ReRAM Array
No full textThis work proposes a neuromodulation-inspired spiking neural network using a ReRAM memory. A stashing-merging algorithm is realized to mimic the inherent neuromodulation in humans. While traditional pruning methods remove redundant parts of the network, stashing excludes well-trained neurons while training and restores all neurons at the end of training. This approach exhibits energy-efficient training in the context of a spiking neural network (SNN) since well-trained neurons can be easily identified using the spike count. The idea is validated using a ReRAM-based SNN with 10 conductance levels and performs close to a traditional artificial neural network (ANN) on an MNIST classification workload
A Soft Error Self-Resilience Radiation-Hardened 14T SRAM for Aerospace Applications
No full textVarious charged particles in space threaten memory circuit integrity and dependability, including photons, alpha particles, and high-energy ions outside the Low Earth Orbit region. These particles particularly affect conventional 6T SRAM by disrupting stored bits, leading researchers to explore radiation-hardened SRAM chips and the addition of extra nodes to memory cells to recover lost data. A novel self resilience radiation-hardened 14T (SRRH-14T) SRAM cell with redundant nodes is presented in this work to solve the soft error problem. The suggested SRRH-14T memory performance compared to well-known radiation-hardened cells, such as 6T-SRAM, Quatro-10T, SEA-14T, RH-14T, QCCS-12T, and RRS-14T. The proposed SRRH-14T memory cell applies to a minimal sensitive node layout area separation to protect against multiple node interruptions. Additionally, the proposed SRRH-14T demonstrates performance enhancements of 1.22x, 1.03x, 1.09x, 1.06x, and 1.02x relative to 6T-SRAM, Quatro-10T, SEA-14T, RH-14T, and RRS-14T, respectively
DETERMINING TIME-DEPENDENT CONVECTION AND DENSITY TERMS IN A CONVECTION-DIFFUSION EQUATION USING PARTIAL DATA
No full textThis article studies an inverse boundary value problem for the time-dependent convection-diffusion equation. We use the nonlinear Carleman weight to uniquely recover the time-dependent convection term and time-dependent density coefficient. Nonlinear weight allows us to prove the uniqueness of the coefficients by making measurements on possibly a small subset of the boundary. We show that the convection term and the density coefficient can be recovered up to the natural gauge from the knowledge of the Dirichlet to Neumann map measured on a small open subset of the boundary
Asynchronous real-time learning in spiking neural network using 3-terminal resistance random access memory
No full textSpiking Neural Networks, inspired by the human brain, are promising as they attempt to solve real-life complex problems, such as pattern recognition, at low energy consumption. Resistance Random Access Memory (RRAM) crossbar array to simulate synaptic weight dynamics, combined with external neuron control circuits, presents a promising approach. The crossbar array of the multilevel resistive memory supports more than two states (LRS and HRS), enhancing RRAM's functionality for analog signals and enabling brain-like processing. However, Reading utilizes low voltage to maintain conductance stability, while writing requires high voltage. Hence, a simultaneous, asynchronous read-write, akin to the brain, remains a significant challenge. Although various solutions exist, a simple, areaefficient solution with low circuit overhead is still challenging. In this paper, a 3-terminal Pr0.7Ca0.3MnO3 (PCMO) RRAM is proposed to enable simultaneous writing and reading, overcoming read-write conflicts of two-terminal RRAM. The typical two terminals of resistive 3T-RRAM are used for writing, and the third terminal is for reading, ensuring real-time asynchronous learning operation. Such an SNN with real-time learning can be advantageous as it reduces circuit overhead and the learning time
Dephasing enabled fast charging of quantum batteries
No full textWe propose and analyze a universal method to obtain fast charging of a quantum battery by a driven charger system using controlled, pure dephasing of the charger. While the battery displays coherent underdamped oscillations of energy for weak charger dephasing, the quantum Zeno freezing of the charger energy at high dephasing suppresses the rate of transfer of energy to the battery. Choosing an optimum dephasing rate between the regimes leads to a fast charging of the battery. We illustrate our results with the charger and battery modeled by either two-level systems or harmonic oscillators. Apart from the fast charging, the dephasing also renders the charging performance more robust to detuning between the charger, drive, and battery frequencies for the two-level systems case
The Bull and the Bear: Summarizing Stock Market Discussions
No full textStock market investors debate and heavily discuss stock ideas, investing strategies, news and market movements on social media platforms. The discussions are significantly longer in length and require extensive domain expertise for understanding. In this paper, we curate such discussions and construct a first-of-its-kind of abstractive summarization dataset. Our curated dataset consists of 7888 Reddit posts and manually constructed summaries for 400 posts. We robustly evaluate the summaries and conduct experiments on SOTA summarization tools to showcase their limitations. We plan to make the dataset publicly available. The sample dataset is available here: https://dhyeyjani.github.io/RSMC. � 2022 Elsevier B.V., All rights reserved
PIC-RAM: Process-Invariant Capacitive Multiplier Based Analog in Memory Computing in 6T SRAM
No full textIn-Memory Computing (IMC) is a promising approach to enabling energy-efficient Deep Neural Network-based applications on edge devices. However, analog domain dot product and multiplication suffers accuracy loss due to process variations. Furthermore, wordline degradation limits its minimum pulsewidth, creating additional non-linearity and limiting IMC's dynamic range and precision. This work presents a complete end-to-end process invariant capacitive multiplier based IMC in 6T-SRAM (PIC-RAM). The proposed architecture employs the novel idea of two-step multiplication in column-major IMC to support 4-bit multiplication. The PIC-RAM uses an operational amplifier-based capacitive multiplier to reduce bitline discharge allowing good enough WL pulse width. Further, it employs process tracking voltage reference and fuse capacitor to tackle dynamic and post-fabrication process variations, respectively. Our design is compute-disturb free and provides a high dynamic range. To the best of our knowledge, PIC-RAM is the first analog SRAM IMC approach to tackle process variation with a focus on its practical implementation. PIC-RAM has a high energy efficiency of about 25.6 TOPS/W for 4-bit� 4-bit multiplication and has only 0.5% area overheads due to the use of the capacitance multiplier. We obtain 409 bit-wise TOPS/W, which is about 2� better than state-of-the-art. PIC-RAM shows the TOP-1 accuracy for ResNet-18 on CIFAR10 and MNIST is 89.54% and 98.80% for 4bit�4bit multiplication. � 2023 Elsevier B.V., All rights reserved
