7294 research outputs found
Sort by
An All-Digital Clock Frequency Caputring Circuitry For NRZ Data Communications
Get PDFA new all-digital circuit scheme for capturing the frequency of an NRZ data stream is described. The proposed scheme is capable of retiming the output clock with the received data within two bit transitions. The absence of analog filters or other analog blocks gives it a much smaller area than conventional circuitry. Also, being fully-digital, it can be described, simulated and synthesized using hardware description languages and be ported to any technology (thus supporting system on a chip designs). Circuit operation and performance was demonstrated using a 0.13 mum, 1.2 V CMOS technology and T-Spicereg simulations
Interconnect-Efficient LDPC Code Design
Get PDFIn this paper, we present a new, hardware-oriented technique for designing Low Density Parity Check (LDPC) codes. The technique targets to achieve an interconnect-efficient architecture that reduces the area and delay of the decoder implementation while maintaining good error correction performance. With a fully parallel implementation of the LDPC decoder, the proposed design assumes a constraint on the interconnect wire length which has a direct impact on the maximum signal delay and power dissipation. Furthermore, this design approach is shown to lower interconnect routing congestion, and hence reduce the chip area and maximize chip utilization
On Optimizing Backoff Procedure to Enhance Throughput and Fairness For Wireless LANs
Get PDFThere is more demand on the services provided by the Wireless devices complying with the IEEE 802.11 standard. Much research is going on to enhance the distributed coordination function (DCF) of the IEEE 802.11 as to support quality of service (QoS) requirements needed by real time services. This is achieved by enhancing the throughput, delay characteristics, and fairness properties of the DCF. The throughput of DCF degrades in high loaded situations. In this paper, we propose and evaluate a novel algorithm to enhance the backoff procedure of DCF. The new algorithm capitalizes on the need to reduce collisions especially when the network is congested. Therefore, the algorithm attempts to adaptively control the DCF contention window in order to alleviate congestion. Evaluation results indicate that better throughput and delay figures are obtained using the proposed algorithm. In addition the algorithm also achieves good fairness compared to DCF
Interconnect-Efficient LDPC Code Design
Get PDFIn this paper, we present a new, hardware-oriented technique for designing Low Density Parity Check (LDPC) codes. The technique targets to achieve an interconnect-efficient architecture that reduces the area and delay of the decoder implementation while maintaining good error correction performance. With a fully parallel implementation of the LDPC decoder, the proposed design assumes a constraint on the interconnect wire length which has a direct impact on the maximum signal delay and power dissipation. Furthermore, this design approach is shown to lower interconnect routing congestion, and hence reduce the chip area and maximize chip utilization
Evolutionary Algorithms for VLSIMultiobjective Netlist Partitioning
Get PDFAbstract. The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to molecular biology. The interest in finding an optimal partition especially in VLSI has been a hot issue in recent years. In VLSI circuit partitioning, the problem of obtaining a minimum cut is of prime importance. With current trends, partitioning with multiple objectives which includes power, delay and area, in addition to minimum cut is in vogue. In this paper, we engineer three iterative heuristics for the optimization of VLSI netlist bi-Partitioning. These heuristics are based on Genetic Algorithms (GAs), Tabu Search (TS) and Simulated Evolution (SimE). Fuzzy rules are incorporated in order to handle the multiobjective cost function. For SimE, fuzzy goodness functions are designed for delay and power, and proved efficient. A series of experiments are performed to evaluate the efficiency of the algorithms. ISCAS-85/89 benchmark circuits are used and experimental results are reported and analyzed to compare the performance of GA, TS and SimE. Further, we compared the results of the iterative heuristics with a modified FM algorithm, named PowerFM, which targets power optimization. PowerFM performs better in terms of power dissipation for smaller circuits. For larger sized circuits SimE outperforms PowerFM in terms of all three, delay, number of net cuts, and power dissipation. Keywords: Genetic Algorithms, Tabu Search, Simulated Evolution, multiobjective, Fuzzy Logic, Netlist partitioning
Integrated Microstrip Feed Network for Phased Array Antenna
Get PDFFerromagnetic material is widely used to realize the phase shift section of a phased array antenna. In this paper, the performance of a microstrip array feeder with integrated phase-shifter, designed on a transversely magnetized ferrite substrate, is described. Calculated differential phase shift and its tuning properties are presented and compared with the results obtained from a commercial CAD tool. The simulated reflection and transmission response of the integrated array feeder is corroborated by experimental data
Efficient Sample Rate Conversion for Software Radio Systems
No full textAn efficient sample rate conversion (SRC) method for software radio (SWR) systems is proposed. The proposed method modifies conventional single- or multistage SRC processes such that the computation of the output of a particular stage is performed in a hierarchical fashion. This SRC method consumes fewer computations than traditional SRC methods over a range of SRC factors and is especially suitable for SWR base station transmitters. The computational requirements of the proposed SRC method and conventional SRC methods are compared and simulation results of the proposed method are discussed
