2199 research outputs found
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An Associative Static and Dynamic Convex Hull Algorithm
No full texthttps://kent-islandora.s3.us-east-2.amazonaws.com/node/16806/87473-thumbnail.jpgThis paper presents a new static and dynamic recursive parallel algorithm for the convex hull problem. This algorithm is a parallel adaptation of the Graham scan and Quick Hull algorithms. The computational model selected for this algorithm is the associative computing model (ASC) which supports massive parallelism through the use of data parallelism and constant time associative search and maximum functions. Also, ASC can be supported on existing SIMD computers. The static algorithm requires O(n) space, O(log n) average case running time, and O(n) worst case running time. If O(log n) ISs are used the, static algorithm should have an average running time of O(log log n).</p
Implementing Associative Search and Responder Resolution
No full texthttps://kent-islandora.s3.us-east-2.amazonaws.com/node/16623/87395-thumbnail.jpgIn a paper presented last year at WMPP\u2701 [Walker01], we described the initial prototype of an associative processor implemented using field-programmable logic devices (FPLDs). That paper presented an overview of the design, and concentrated on the processor\u27s instruction set and its implementation using FPLDs. This paper describes the implementation of the processor\u27s associative operation -- associative searching and responder resolution -- in more detail.</p
Tractable Real-Time Air Traffic Control Automation
No full texthttps://kent-islandora.s3.us-east-2.amazonaws.com/node/17411/87500-thumbnail.jpgA different paradigm is needed for real-time command and control (C&C) problems. Past approaches, using multiprocessors (MP), for real-time computing have had great difficulty in meeting real problem requirements. We review some reasons why C&C problems that require a solution on a MP architecture may be intractable, and then show an architecture where these reasons for intractability are nonexistent. We describe a polynomial time solution to the air traffic control (ATC) problem, which is a typical C&C problem. This solution uses a static, non-preemptive table driven schedule using a SIMD architecture called an associative processor (AP). The AP is an ideal processor for set and database operations since its single thread instruction stream can operate on an entire set of data with each instruction. The AP eliminates multi-thread instructions, which account for much of the MP intractability mentioned above.</p
TechKNOW Volume 8, Issue 2
No full texthttps://kent-islandora.s3.us-east-2.amazonaws.com/techknow/24/thumbnail.jp
Using the UML to Describe the BSP Model of Parallel Computation
No full texthttps://kent-islandora.s3.us-east-2.amazonaws.com/node/17401/87328-thumbnail.jpgA Unified Modeling Language (UML) description of the BSP model of parallel computation is presented. This UML description identifies BSP classes and objects and specifies various object and inter-object relationships, dependencies, and behaviors. This was achieved by describing various views of the BSP model using many of the UML structural and behavioral diagrams. The use to the UML to describe the BSP model has been highly effective for further parallel modeling techniques, comparisons to other parallel models, BSP parallel system software research, and BSP algorithm development.</p
The Burr Spring 2002
No full texthttps://kent-islandora.s3.us-east-2.amazonaws.com/theburr/32/thumbnail.jp
Implementing associative processing: Rethinking earlier architectural decisions
No full texthttps://kent-islandora.s3.us-east-2.amazonaws.com/node/16624/87397-thumbnail.jpgThis paper describes an initial design of an associative processor for implementation using field-programmable logic devices (FPLDs). The processor is based loosely on earlier work on the STARAN computer, but updated to reflect modern design practices. We also draw on a large body of research at Kent State on the ASC and MASC models of associative processing, and take advantage of an existing compiler for the ASC model. The resulting design consists of an associative array of 8-bit RISC Processing Elements (PEs), operating in byte-serial fashion under the control of an Instruction Stream (IS) Control Unit that can execute assembly language code produced by a machine-specific back-end compiler.</p
TechKNOW, Volume 7, Issue 3
No full texthttps://kent-islandora.s3.us-east-2.amazonaws.com/techknow/28/thumbnail.jp
Occopodian 2001
No full texthttps://kent-islandora.s3.us-east-2.amazonaws.com/cpmyearbooks/57/thumbnail.jp
Writing Center Review Volume 6 Spring 2001
No full texthttps://kent-islandora.s3.us-east-2.amazonaws.com/wcr/vol6/iss1/1/thumbnail.jp