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Genomic and Replicative Characterization of a Novel Nora-like Picornavirus Infecting the Araneae Order
Get PDFThe Picornavirales order is characterized for having a genome composed of a single reading frame. However, viral evolution has shown genome organization is not conserved within viral supergroups. Noraviridae is a family in the Picornavirales order, however these viruses are unique for being the only picornaviruses with genomes composed of four reading frames. While nora viruses were initially found only in Drosophila flies, new studies presume to show nora virus presence in other invertebrates. Picornaviruses and coronaviruses show protein homology and have common ancestors, but the genome organization of coronaviruses is present in multiple reading frames that are transcribed in a segmented genome strategy. Our research believed that due to the genome organization of nora viruses, segmented genome transcription was also used, yet we have seen this is not the case. We have identified novel nora-like viruses in a spider silk transcriptome, but their genome characterization remains unknown. We find that while not all viruses in our transcriptome belong in Noraviridae, six viruses do show the evolution of the genome organization in Noraviridae. We argue that these nora viruses do not undergo segmented genome replication due to the presence of IRES elements and ribosomal frameshifting in nora viral genomes. Rather, the fragmentation of Noraviridae into multiple reading frames appears to be an example of convergent evolution to lose ORF3. These results build on the research that nora viruses can infect other invertebrates, while providing new insight into the function of ORF3 and the evolution of genome organization in the Picornavirales order
Design of Power-Efficient Passive Amplification Successive Approximation Analog-to-Digital Converter and Matrix-Based Digital Foreground Calibration Technique
No full textIn recent times, there has been a surge in demand for portable electronic gadgets like biomedical products, smartphones, and smart devices. The batteries of these devices provide limited power which emphasizes the necessity to conduct research that leads to energy-efficient IC chip designs for such portable instruments. Notably, an important area of concern centers on developing high-resolution ADCs capable of wide bandwidth utilization while conserving energy. Considering its role as one of the primary components employed in processing signals after filters and mixers and converting them into a digital format compatible with microprocessors/controllers, the importance placed on minimizing this block���s power consumption cannot be overstated because it is used frequently across wireless communication systems.
Two projects comprise this study, both of which focus on the design of analog and mixed-signal
circuits with power efficiency in mind. The primary research involves Successive Approximation
Analog-to-Digital Converters, which have become increasingly popular in mobile technology due to their low energy consumption, compact size, and high Signal-to-Noise-and-Distortion Ratio measuring between 60dB to 70 dB. However, SAR ADC performance is limited by a trade-off among linearity, speed, and noise; boosting capacitive Digital-to-Analog Converter array size can improve linearity and will also decrease switches noise at the expense of incomplete settling for Capacitor Array DAC and the reference voltage. As a result, many approaches including the Noise Shaping Technique were introduced lately aiming at mitigating these issues.
In this dissertation, a new approach is proposed to improve the signal to noise ratio through passive amplification without engaging active components. This advancement enables an additional bit resolution while maintaining the original signal bandwidth and ADC switching rate intact. Furthermore, a new design for low-power 150MS/s successive approximation ADCs with 12-bit precision is introduced that reduces CDAC array size via voltage generator employment. Additionally, an offset cancellation technique for compensating comparator mismatch errors is proposed.
The findings reveal that the proposed design for ADC utilizes 1.22mA and 0.584mA when powered by supply voltages of 1.32V and 2.5V, respectively. The ADC reference generation section is powered by a 2V voltage reference, and it consumes a current of 594 ��A. The system proposed is expected to attain SNDR around 62dB with a 10MHz sinusoidal test vehicle using an ADC architecture designed in a 40nm CMOS technology with an active area of about 0.035 mm2. Further, this architecture is expected to achieve a Walden figure-of-merit approximately 25fj/conv-step while maintaining Schrier FOM rates around 165dB.
The second project is about a foreground matrix-based digital calibration technique that is proposed for high-performance ADCs to reduce performance loss due to transistor limitations and unavoidable converter component mismatches. A set of calibration coefficients is obtained during foreground calibration and then used during normal operation to correct the ADC output using conventional digital circuitry. The validity of a calibration technique is confirmed by assessing it on a 12-bit SAR ADC with an on-chip sinusoidal input signal generator operating at 350 MS/s at 10 MHz. The simulation results demonstrate that the proposed methods to calibrate random capacitive DAC array elements mismatch successfully improve both differential non-linearity and integral non-linearity, showing a noticeable enhancement in the signal-to-distortion ratio/spurious free dynamic range. Additionally, applying this technique optimizes a 40nm TSMC CMOS fabricated Pipeline ADCs��� performance operating at 260 MS/s with up to 68.23dB SNDR and 85.82dB SFDR for low frequency sinusoidal inputs
