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Temperature-Constrained Fixed-Outline Floorplanning for 3D Ics
No full text[[abstract]]Three-dimensional (3D) ICs are produced by stacking multiple dies and delivering inter-die signals with Through-Silicon Vias (TSVs). Typically, TSVs which deliver signals among dies are called signal TSVs, while those enhancing heat dissipation are called thermal TSVs. In this paper we present a temperature-constrained fixed-outline 3D-IC floorplanner which also simultaneously places signal and thermal TSVs to benefit wirelength and temperature reduction. Encouraging experimental results are shown to demonstrate the effectiveness and efficiency of our floorplanner.[[fileno]]2030229030060[[department]]資訊工程學
工學院榮譽榜
No full text[[abstract]]薛敬和教授榮獲日本高分子學會SPSJ之International Award
中華民國顯微鏡學會第21屆年會暨第23屆學術研討會[[fileno]]202_JA01_2003_n10_p2
