Ruhr-Universität Bochum (RUB): Open Journal Systems
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CHERI-Crypt: Transparent Memory Encryption on Capability Architectures
Get PDFCapability architectures such as CHERI (Capability Hardware Enhanced RISC Instructions) are an emerging technology designed to provide memory safety protection at the hardware level and are equipped to eradicate approximately 70% of the current software vulnerability attack surface. CHERI is an instruction set architecture extension and has been applied to a small number of processors, including various versions of RISC-V. One of the benefits of CHERI is that it inherently provides segregation or compartmentalisation of software, making it suitable for supporting other types of applications such as Trusted Execution Environments, where sensitive data and computation is conducted inside a secure enclave, away from the rest of the untrusted operating system and services. To prevent untrusted software from accessing these compartments or secure regions of memory CHERI uses the mechanism of sealed capabilities. Trusted execution environments however, have been proven vulnerable to not just software-based attacks, but hardware attacks as well. In this paper we present our CHERI-Crypt design, an encryption engine extension to a CHERI-RISC-V 32-bit processor, for transparent memory encryption of sealed CHERI capabilities to additionally protect sensitive data in memory against physical hardware attacks. We show that our CHERI-Crypt design can run an enclave test program within an encrypted CHERI seal and invoke process, requiring 626 additional clock cycles with a batch size of 32 bytes. Adding CHERI-Crypt reduces the maximum frequency of the base CPU by only 6 MHz, and requires approximately 3.5x more flip flops and LUTs
Optimal Dimensionality Reduction using Conditional Variational AutoEncoder
Get PDFThe benefits of using Deep Learning techniques to enhance side-channel attacks performances have been demonstrated over recent years. Most of the work carried out since then focuses on discriminative models. However, one of their major limitations is the lack of theoretical results. Indeed, this lack of theoretical results, especially concerning the choice of neural network architecture to consider or the loss to prioritize to build an optimal model, can be problematic for both attackers and evaluators. Recently, Zaid et al. addressed this problem by proposing a generative model that bridges conventional profiled attacks and deep learning techniques, thus providing a model that is both explicable and interpretable. Nevertheless the proposed model has several limitations. Indeed, the architecture is too complex, higher-order attacks cannot be mounted and desynchronization is not handled by this model. In this paper, we address the first limitation namely the architecture complexity, as without a simpler model, the other limitations cannot be treated properly. To do so, we propose a new generative model that relies on solid theoretical results. This model is based on conditional variational autoencoder and converges towards the optimal statistical model i.e. it performs an optimal attack. By building on and extending the state-of-the-art theoretical works on dimensionality reduction, we integrate into this neural network an optimal dimensionality reduction i.e. a dimensionality reduction that is achieved without any loss of information. This results in a gain of O(D), with D the dimension of traces, compared to Zaid et al. neural network in terms of architecture complexity, while at the same time enhancing the explainability and interpretability. In addition, we propose a new attack strategy based on our neural network, which reduces the attack complexity of generative models from O(N) to O(1), with N the number of generated traces. We validate all our theoretical results experimentally using extensive simulations and various publicly available datasets covering symmetric, asymmetric pre and post-quantum cryptography implementations
Design and Implementation of a Physically Secure Open-Source FPGA and Toolchain
Get PDFThe increasing prevalence of security breaches highlights the importanceof robust hardware security measures. Among these breaches, physical attacks– such as Side-Channel Analysis ( SCA) and Fault Injection (FI ) attacks – posea significant challenge for security-sensitive applications. To ensure robust systemsecurity throughout its lifecycle, hardware security updates are indispensable alongsidesoftware security patches. Programmable hardware plays a pivotal role in establishinga robust hardware root-of-trust, serving to effectively mitigate various hardwaresecurity threats. In this paper, we propose a methodology for the design of areconfigurable fabric and the corresponding mapping toolchain, specifically tailoredto hardware security. This approach offers resistance to various malicious physicalattacks, including SCA and FI , addressing each threat individually. As a case study,we propose a resulting fabric that implements a combination of first-order BooleanMasking and hiding countermeasures to provide strong protection against SCA attacksand enables the detection of fault injection attempts. In particular, we present howreconfigurable secure gadgets can be realized employing a reformed variant of theLUT-based Masked Dual-Rail with Pre-charge Logic (LMDPL) hardware maskingscheme and a modified version of Wave Dynamic Differential Logic ( WDDL) tobe composed into a fabric. We also show how any basic Hardware DescriptionLanguage ( HDL) design is automatically mapped to the primitives of our fabric,embedding provable hardware security, and bypassing the necessity for hardwaresecurity proficiency in this process. It is worth mentioning that our fabric requiresapproximately 85% less area to map a secure design compared to conventional FieldProgrammable Gate Arrays ( FPGAs). A practical security evaluation of our securefabric implementation on a real FPGA target board, using Test Vector LeakageAssessment (TVLA), demonstrated no SCA leakage over 100 million traces
Let’s DOIT: Using Intel’s Extended HW/SW Contract for Secure Compilation of Crypto Code
Get PDFIt is a widely accepted standard practice to implement cryptographic software so that secret inputs do not influence the cycle count. Software following this paradigm is often referred to as “constant-time” software and typically involves following three rules: 1) never branch on a secret-dependent condition, 2) never access memory at a secret-dependent location, and 3) avoid variable-time arithmetic operations on secret data. The third rule requires knowledge about such variable-time arithmetic instructions, or vice versa, which operations are safe to use on secret inputs. For a long time, this knowledge was based on either documentation or microbenchmarks, but critically, there were never any guarantees for future microarchitectures. This changed with the introduction of the data-operand-independent-timing (DOIT) mode on Intel CPUs and, to some extent, the data-independent-timing (DIT) mode on Arm CPUs. Both Intel and Arm document a subset of their respective instruction sets that are intended to leak no information about their inputs through timing, even on future microarchitectures if the CPU is set to run in a dedicated DOIT (or DIT) mode.In this paper, we present a principled solution that leverages DOIT to enable cryptographic software that is future-proof constant-time, in the sense that it ensures that only instructions from the DOIT subset are used to operate on secret data, even during speculative execution after a mispredicted branch or function return location. For this solution, we build on top of existing security type systems in the Jasmin framework for high-assurance cryptography.We then use our solution to evaluate the extent to which existing cryptographic software built to be “constant-time” is already secure in this stricter paradigm implied by DOIT and what the performance impact is to move from constant-time to future-proof constant-time
A commentary on “What is it like to be a tetrachromat?” by Michael Newall
Get PDFAnalytical examinations of subjective experience are hampered by the first-person limitation described by Nagel (1974) in “What is it like to be a bat?”. This comment compares two examinations on the nature of subjective experience: Michael Newall’s (2025) analysis of tetrachromatic colour perception and Jordi Galiano-Landeira and Núria Peñuelas’ (2025) exploration of AI phenomenological consciousness within panpsychism. Newall examined whether tetrachromats perceive entirely novel colours or finer gradations of known ones, using analogies with dichromats and empirical evidence. Newall argued for the possibility of novel colour experiences. Galiano-Landeira and Peñuelas proposed that the analog/non-analog distinction is user-dependent, implying that AI could be phenomenologically conscious despite digital information processing. Although both works stemmed from completely different starting points, they emphasize the continuity of experience besides the perceptual resolution, questioning anthropocentric and chauvinistic biases in phenomenal consciousness studies. The structuralist perspective on colour quality spaces is also discussed to further delve into tetrachromatic perception, suggesting that tetrachromats might experience both finer gradations and novel colours
Considerations Concerning Diversifying Curriculum
Get PDFPhilosophy has long been one of the last holdouts against efforts to rethink curriculum. Recent-ly and globally, however, philosophy departments, curricular specialists and individual philoso-phy teachers have begun to make serious efforts at curricula diversification. This paper focuses on two main questions in this regard. First, why diversify? While it’s often assumed to be obvi-ous, many of the justifications given by philosophy departments have missed some of the best arguments in favor of these efforts. Secondly, this paper looks at what a diversification of a phi-losophy curriculum should consider. This includes expanding the canon of what should be taught, rethinking what counts as philosophy and finally, exploring new methods for teaching and evaluating philosophy learning
Review: Stancu, Andrea Susanne: Deutsche Landeskunde an rumänischen Hochschulen.
No full textRezension: Stancu, Andrea Susanne (2024): Deutsche Landeskunde an rumänischen Hochschulen.Review: tancu, Andrea Susanne (2024): Deutsche Landeskunde an rumänischen Hochschulen
Flipper: Rowhammer on Steroids
Get PDFThe density of memory cells in modern DRAM is so high that frequently accessing a memory row can flip bits in nearby rows. That effect is called Rowhammer, and an attacker can exploit this phenomenon to flip bits by rapidly accessing the contents of nearby memory rows. In recent years, researchers have developed sophisticated exploits based on this vulnerability, which enable privilege escalation on desktop computers, mobile devices, and even cloud systems without requiring any software vulnerability. However, rows are not equally vulnerable to Rowhammer. Therefore, an attacker has to massage the memory, for instance, with Page Table Entry (PTE) spraying, to increase the chance of successful exploitation. More bit flips mean the attacks become easier and faster to conduct.
In this paper, we present Flipper, a Rowhammer amplification attack against DDR3, consisting of two components: cmpIST exploits the cmpsb and repe x86 instructions to get DRAM access with higher frequency. cmpP AR exploits the effect of hammering in multiple threads, which increases the number of bit flips found in a given time, as shown in previous work. As a result, we can increase the number of bit flips by a factor of 830 on the measured devices, even on systems featuring mitigation techniques, without using administrative privileges. We evaluate our technique on six DDR3 DIMMs. Although DDR3 memory has been superseded by DDR4 and DDR5 memory technologies, it is still widely used in devices that do not require frequent replacement, such as projectors, smart displays, servers, embedded devices, routers, and printers
The Notion of ‘Effortlessness’ in the Dzogchen Commentaries by Nubchen Sangye Yeshe
No full textThe present contribution will seek to explore the notion of effortlessness in the Dzogchen commentaries by Nubchen Sangye Yeshe (ca. 844–mid-tenth century), examining its role as a key theme in the self-understanding of the emergent Dzogchen tradition’s approach to contemplative practice. We will also touch upon the (apparent?) paradox consisting of learning the meditative skill of uncontrived effortlessness, where the process of meditative training and the content or ideal of this training are supposed to coalesce
THF: Designing Low-Latency Tweakable Block Ciphers
No full textWe introduce the Three-Hash Framework (THF), a new instantiation of the LRW+ paradigm that employs three hash functions to process tweak inputs. We prove that THF achieves beyond-birthday-bound security under standard assumptions. By extending the general practical cryptanalysis framework to the multiple-tweak setting, we further demonstrate that THF offers balanced resistance to both singleand multiple-tweak attacks, thereby enabling the potential for lower latency compared to existing constructions. Building on this framework, we design Blink, a family of tweakable block ciphers optimized for ultra-low latency. Blink features logarithmic-depth Toeplitz-based hashing, which ensures efficient diffusion and scalability with varying tweak lengths. Our cryptanalysis shows that Blink achieves strong security with fewer rounds, while hardware evaluations confirm its superior latency performance. Notably, Blink maintains comparable latency even when the tweak length is doubled, underscoring the scalability advantage of THF