1,721,080 research outputs found
An F-algebra for analysing information leaks in the presence of glitches
Full text linkThis report deals with the problem of identifying the potential correlations between the observable power consumption of a digital circuit and its inputs, when the operating conditions of the circuit involve a logic hazard (also known as glitch). This problem is of utmost importance when the circuit is a cryptographic primitive that must ensure that secret input data (e.g., keys) does not leak.
We present a universal algebra construction that allows to derive a set of artefacts from a digital circuit among which a conservative estimate of the Boolean expression that the circuit might leak as well as the extended input/output correlation matrix [1]. This allows the evaluation of the robustness against side channel attacks through a set of constructions that fall under the umbrella of robust probing security [2]. We believe that such a formalisation is well suited for CAD synthesis tools to help the design of more robust cryptographic primitives
ConceptOS: A Micro-Kernel Approach to Firmware Updates of Always-On Resource-Constrained Hubris-Based IoT Systems
No full textThis article investigates and validates an approach to perform component-level updates with live state transfer in an existing embedded operating system for flash-based microcontrollers. The resulting proof of concept, called ConceptOS, allows live component updates and requires 21% less space than a conventional update with an overhead comparable to a single page-erase time. At the same time, we reduced the system unavailability by 53.8%. This article will describe the relevant state-of-the-art, background information, and the proposed approach in terms of memory organization, compile-time representation, and component delivery protocol. Experiments will compare the actual memory requirements and overhead with respect to a conventional OTA approach
Multi-Objective Design Space Exploration of Embedded Systems
No full textIn this paper, we address the problem of the efficient exploration of the architectural design space for parameterized embedded systems. The exploration problem is multi-objective (e.g., energy and delay), so the main goal of this work is to find a good approximation of the Pareto-optimal configurations representing the best energy/delay trade-offs by varying the architectural parameters of the target system. In particular, the paper presents a Design Space Exploration (DSE) framework to simulate the target system and to dynamically profile the target applications. In the proposed DSE framework, a set of heuristic algorithms have been analyzed to reduce the overall exploration time by computing an approximated Pareto set of configurations with respect to the selected figures of merit. Once the approximated Pareto set has been built, the designer can quickly select the best system configuration satisfying the constraints. Experimental results, derived from the application of the proposed DSE framework to a superscalar architecture, show that the exploration time can be reduced by three orders of magnitude with respect to the full search approach, while maintaining a good level of accuracy
Symbolic Analysis of Higher-Order Side Channel Countermeasures
Full text linkIn this paper, we deal with the problem of efficiently assessing the higher order vulnerability of a hardware cryptographic circuit. Our main concern is to provide methods that allow a circuit designer to detect early in the design cycle if the implementation of a Boolean-additive masking countermeasure does not hold up to the required protection order. To achieve this goal, we promote the search for vulnerabilities from a statistical problem to a purely symbolical one and then provide a method for reasoning about this new symbolical interpretation. Eventually we show, with a synthetic example, how the proposed conceptual tool can be used for exploring the vulnerability space of a cryptographic primitive
Power-Performance System-Level Exploration of a MicroSPARC2-based Embedded Architecture
No full textThis paper describes the architectural exploration of the system-level parameters for a MicroSPARC2-based embedded system. The overall goal of the exploration task is to quickly identify the best architecture of the embedded system in terms of both energy and delay parameters, avoiding the comprehensive analysis of the architectural design space. The Energy-Delay Product (EDP) has been adopted as the evaluation metric to compare the alternative architectures in terms of different cache memory and bus subsystems. The exploration phase adopts an iterative local-search algorithm based on the sensitivity analysis of the cost function with respect to the tuning parameters of system architecture. The exploration targets the architectural optimisation of the parameters related to the cache memory and the bus sub-systems of an embedded architecture based on the MicroSPARC2 architecture executing the set of Mediabench benchmarks for multimedia applications. The experimental results ha ve shown a reduction up to nine orders of magnitude ofthe n umber of design alternatives analyzed during the exploration phase
A Variability-Aware Robust Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific Constraints
No full textManufacturing process variation is dramatically becoming one of the most important challenges related to power and performance optimization for sub-90nm CMOS technologies. Process variability impacts the optimization of the target system metrics, that is, performance and energy consumption by introducing fluctuations and unpredictability. Besides, it impacts the parametric yield of the chip with respect to application level constraints by reducing the number of devices working within normal operating conditions.
The impact of variability on systems with stringent application-specific requirements (such as portable multimedia and critical embedded systems) is much greater than on general-purpose systems given the emphasis on predictability and reduced operating margins. In this market segment, failing to address such a problem within the early design stages of the chip may lead to missing market deadlines and suffering greater economic losses.
In the context of a design space exploration framework for supporting the platform-based design approach, we address the problem of robustness with respect to manufacturing process variations. First, we apply Response Surface Modeling (RSM) techniques to enable an efficient evaluation of the statistical measures of execution time and energy consumption for each system configuration. Then, we apply a robust design space exploration framework to afford the problem of the impact of manufacturing process variations onto the system-level metrics and consequently onto the application-level constraints. We finally provide a comparison of our design space exploration technique with conventional approaches on two different case studies
On the spectral features of robust probing security
Full text linkIn this work we provide a spectral formalization of non-interference in the presence of glitches. Our goal is to present new theoretical and practical tools to reason about robust-d-probing security. We show that the current understanding of extended probes lends itself to probes that participate, during gadget composition, to the creation of additional extended probes. In turn, this enables a natural extension of non-interference definitions into robust ones to build a new reasoning framework that can formally explain some semi-formal results already appeared in the past and be used to synthesize new robust-d-SNI gadgets
Interruptible Remote Attestation of Low-End IoT Microcontrollers via Performance Counters
No full textRemote attestation is a method used in distributed systems to detect integrity violations on a target device (prover) through a challenge-response protocol initiated by a verifier device. The prover calculates a hash of its memory, which is compared to a known good state hash by the verifier. We propose a novel technique, called Counters Help Against Roving Malware (CHARM), which uses hardware performance counters on the prover's side and machine learning on the verifier's side to make interruptible remote attestation feasible, even for constrained microcontrollers. We will demonstrate the effectiveness of various machine learning tools and data manipulation techniques on prediction accuracy in a variety of scenarios
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip
No full textToday’s System on Chip (SoC) technology can achieve unprecedented computing speed that is shifting the IC design bottleneck from computation capacity to communication bandwidth and flexibility. This chapter presents an innovative methodology for automatically generating the energy models of a versatile and parametric on-chip communication IP (STBus). Eventually, those models are linked to a standard SystemC simulator, running at BCA and TLM abstraction level. To make the system power simulation fast and effective, we enhanced the STBus class library with a new set of power profiling features (“Power API”), allowing performing power analysis either statically (i.e.: total avg. power) or at simulation runtime (i.e.: dynamic profiling). In addition to random patterns, our methodology has been extensively benchmarked with the high-level SystemC simulation of a real world multi-processor platform (MPARM). It consists of four ARM7TDMI processors accessing a number of peripheral targets (including several banks of SRAMs, Interrupt’s slaves and ROMs) through the STBus communication infrastructure. The power analysis of the benchmark platform proves to be effective and highly correlated, with an average error of 2% and a RMS of 0.015 mW vs. the reference (i.e. gate level) power figures. The chapter ends presenting a new and effective methodology to minimize the Design of Experiments (DoE) needed to characterize the above power models. The experimental figures show that our DoE optimization techniques are able to trade off power modeling approximation with characterization cost, leading to a 60% average reduction of the sampling space, with 20% of maximum error
Low Effort, High Accuracy Network-on-Chip Power Macro ModelingIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
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