4,151 research outputs found

    Ka-band low noise amplifier using standard 0.19 mu m CMOS technology

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    [[abstract]]A low-power-consumption (26.93 mW) 32 GHz (Ka-band) low noise amplifier (LNA) using standard 0.18 mu m CMOS technology is reported. To achieve sufficient gain, this LNA is composed of three cascaded common-source stages. The output of each stage is loaded with a bandpass (or a highpass) combination of L and C to provide parallel resonance, i.e. to maximise the gain, at the design frequency. This LNA achieved input return loss (S-11) of -13.3 dB, output return loss (S-22) of -13.4 dB, forward gain (S-21) of 10.2 dB and reverse isolation (S-12) of -19.1 dB at 32 GHz. This LNA consumed only a small DC power of 26.93 mW The chip area is only 740 x 500 mu m, excluding the test pads.[[note]]SC

    Design and implementation of a 1.5- to 17-GHz SiGeUWB LNA utilizing multiple-feedback loops and inductive peaking technique

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    [[abstract]]In this paper, we demonstrate a 1.5- to 17-GHZ ultrawideband (UWB) low-noise amplifier (LNA) with small-inductance input inductor and multiple-feedback loops implemented in a 0.35 mu m SiGe BiCMOS technology. A method named inductive peaking, which adds an inductor in series with the base-terminal of the second-stage amplifier to enhance the frequency of the dominant pole, was adopted to improve gain and bandwidth (of the LNA. The measurement results show that very flat gain (S-21) of 8 +/- 0.5 dB was achieved for frequencies between 2 and 15 GHz. In addition, reverse isolation (S-12) lower than -27 dB, input return loss (S-11) and output return loss (S-22 lower than -9 dB, and noise figure lower than 5.5 dB was achieved in the 3.1-10.6 GHz UWB band. The chip area was 775 X 710 mu m(2), excluding the test pads. This LNA drains 7 mA current at supply voltage of 3 V, i.e. it only cansumes 21 mW power. (c) 2007 Wiley Periodicals, Inc.[[note]]SC

    A high-performance 1-7 GHz UWB LNA using standard 0.18 mu m CMOS technology

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    [[abstract]]In this article, we demonstrate a high-peformance 1- to 7-GHz ultra-wideband (UWB) low-noise amplifier (LNA) for UWB system applications implemented in a standard 0.18 mu m CMOS technology. This LNA can also be applied to 1.8/1.9-GHz-band GSM systems, and 2.4/4.9/ 5.2/5.7-GHz-band WLAN systems. The LNA consists of two cascaded stages, in which the pole of the first stage is cancelled by the zero of the second stage over the 1-7 GHz, of interest. In addition, the inductive peaking technique is adopted in the second stage for bandwidth enhancement. This LNA achieved input return loss (S-11) of -10 to -15.3 dB, output return loss (S-22) of -19.4 to -10.3 dB, voltage gain (A(v)) of 13.3 to 14.6 dB, reverse isolation (S-12) of -37.7 to -27.1 dB over the 1- to 7-GHz band of interest. The measured noise figure (NF) was 4.86-4.35 dB over the 2-8.5 GHz band. The measured 1-dB compression point (P-1dB) and third-order inter-modulation point (IIP3) were -13.5 dBm and -3 dBm, respectively, at 6 GHz. The chip area was only 500 mu m x 582 mu m excluding the test pads. This LNA drained 10.4 mA current at supply voltage of 1.5 V, i.e. it only consumed 15.6 mWpower. (C) 2007 Wiley Periodicals, Inc.[[note]]SC

    Wellesly Sh. W. to Mr. James Meredith (2 October 1962)

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    Signed by Wellesly Sh. W.https://egrove.olemiss.edu/mercorr_pro/1531/thumbnail.jp
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