1,790 research outputs found
G.N. Itz: Stadsbouwmeester van Dordrecht 1832-1867
No full textDit boek bespreekt het leven en werk van G.N. Itz, stads bouwmeester van Dordrecht en zijn positie binnen de architectuurstromingen van de eerste helft van de negentiende eeuw. Een tijdvak dat tot nu toe in de architectuurgeschiedenis weinig aandacht heeft gekregen. G.N. Itz heeft vele bouwwerken ontworpen die heden ten dage nog het aanzicht van Dordrecht bepalen. Zo is de Korenbeurs en de Oud-Katholieke Kerk St. Maria Maior van zijn hand. Mede door de vele illustraties geeft dit boek een goed overzicht van de ontwerpen van G.N. Itz.Architectur
Direct numerical simulation of turbulent Couette-Poiseuille flow with zero skin friction
No full textThe near-wall scaling of mean velocity U(y) is addressed for the case of zero skin friction on one wall of a fully turbulent channel flow. The present DNS results can be added to the evidence in support of the conjecture that U is proportional to √yw in the region just above the wall at which the mean shear dU/dy = 0
Tatar folk festivals and traditions through the eyes of a historian. To the 155th anniversary of scholar G.N. Akhmarov.
No full textThe name of Gaynetdin Nedzhmutdinovich Akhmarov (1864–1911) holds a spe-cial place among the scholars of the early 20th century due to his significant and multi-dimensional work. He is an educator, author of textbooks, historian, ethnographer, and public figure. The purpose of the paper is to explore the description of traditional Tatar customs and holidays in G.N. Akhmarov’s works. His historical analysis and explana-tion of the origin and development of folk traditions generates big interest not only in the academic circles, but among a broad audience of readers. The scholar’s works con-tain богатый материал on Tatar festivities. One particular work explores a Tatar wed-ding, which is shown as a national custom that has been formed over the course of many years. In his description of a Tatar wedding, the author provides its historical justification as he relies on his vast knowledge of history. G.N. Akhmarov uses this approach in the analysis of the Tatar holiday Sabantuy. The scholar reveals its history and conducts a comparative historical analysis with holidays of other Turkic peoples. The article exa¬mines the researcher’s view on other traditional festivities of Tatars
Testing of modern semiconductor memory structures
No full textIn this thesis, we study the problem of faults in modern semiconductor memory structures and their tests. According to the 2005 ITRS, the systems on chip (SoCs) are moving from logic and memory balanced chips to more memory dominated devices in order to cope with the increasing application requirements. The embedded memories are expected to utilize more than 60% of the chip area after 2009. In addition, future SoCs are believed to embed memories of increasing capacities. As a result, the overall SoC yield will be dominated by the memory yield. This trend may make the overall yield unacceptable, unless special measures have been taken. In this thesis we propose and classify DRAM specific fault models relevant for the state-of-the-art semiconductor technologies. We also define and validate a set of DRAM targeted march tests. In addition, we propose a methodology for deriving conditions and tests for linked memory faults. We also investigate the detection conditions for linked memory faults when one of the faults involved is an address decoder fault. Finally, we propose various optimizations for test time reduction and/or increased fault coverage. We aimed at high relevancy of the ideas proposed in this thesis. For as far as possible the fault models and the tests presented here are validated using real industrial products. Some of the concepts originally proposed by the author more than 10 years ago are still being widely used by the industry and referred to by the academia. For example, many industrial products did use or are still using March LR, one of the tests derived in this thesis, for testing their (embedded) memories.Electrical Engineering, Mathematics and Computer Scienc
Asuhan Kebidanan Berkelanjutan Pada Ny G.N G3p2a0ah2 Usia Kehamilan 37 Minggu 5 Hari Di Puskesmas Pembantu Lasiana Tanggal 15 Februari S/D 11 April 2024
No full textLatar Belakang : Penyebab kematian ibu di Indonesia didominasi oleh tiga penyebab utama kematian yaitu perdarahan, hipertensi dalam kehamilan dan infeksi. Hal ini terjadi karena minimnya kesadaran dan pengetahuan ibu serta keluarga akan pentingnya pemeriksaan kehamilan secara teratur, masih rendahnya angka persalinan di fasilitas kesehatan, rendahnya pemeriksaan pada masa nifas serta kurangnya askes terhadap fasilitas kesehatan. Sementara itu penyebab angka kematian bayi yaitu dimana masih banyak ibu yang tidak melakukan pemeriksaan ANC dan pertolongan persalinan yang ditolong oleh tenaga kesehatan serta kurangnya kesadaran ibu nifas untuk memeriksakan kesehatan bayinya di fasilitas kesehatan. Tujuan : Mampu menerapkan Asuhan Kebidanan Berkelanjutan pada Ny G.N G3P2A0AH2 Di Puskesmas Pembantu Lasiana Kecamatan Kelapa Lima Kabupaten Kupang Periode 15 Februari s/d 04 April 2024”. Metode : Penelitian menggunakan metode studi penelahan kasus yang terdiri dari unit tunggal, yang berarti penelitian ini dilakukan pada seorang ibu dalam menjalani kehamilan, persalinan, nifas, bayi baru lahir dan keluarga berencana. Lokasi studi kasus di Puskesmas Pembantu Lasiana, subjek studi kasus adalah Ny G.N, dilaksanakan pada tanggal 15 Februari s/d 04 April 2024 dengan menggunakan format asuhan kebidanan pada ibu hamil dengan metode Varney dan pendokumentasian SOAP, Teknik pengumpulan data menggunakan data primer dan data sekunder Hasil dan Pembahasan : Setelah dilakukan asuhan kebidanan berkelanjutan pada Ny. G. N penulis mendapatkan hasil yaitu Ibu melakukan kunjungan sesuai anjuran , dalam pemberian asuhan tidak terdapat penyulit, persalinan berjalan normal serta kunjungan bayi baru lahir dan postpartum berjalan dengan normal dan tidak ada penyulit. Simpulan : Asuhan Kebidanan secara berkelanjutan keadaan pasien baik mulai dari kehamilan sampai pada bayi baru lahir dan KB asuhan dapat diberikan dengan baik
Automated computational modelling for complicated partial differential equations
No full textIn engineering, physical phenomena are often described mathematically by partial differential equations (PDEs), and a commonly used method to solve these equations is the finite element method (FEM). Implementing a solver based on this method for a given PDE in a computer program written in source code can be tedious, time consuming and error prone. Recently, compilers that automatically generate source code from the mathematical representation of a given PDE expressed in a form language have been introduced. This approach to automated mathematical modelling, which is key in the FEniCS Project (\url{http://fenicsproject.org}), has reduced the burden of application developers working with the FEM when it comes to implementing solvers for new models. In this thesis, the automated modelling framework of the FEniCS Project is extended such that discontinuous Galerkin methods can be handled; rapid prototyping of advanced models and applications is possible; and efficiency is maintained also for complex problems in general. The extensions are implemented in various components of the FEniCS framework. For instance, the Unified Form Language (UFL) is extended by adding new abstractions that allow operators pertinent to discontinuous Galerkin methods to be represented in a straightforward fashion. The FEniCS Form Compiler (FFC) is also extended such that code can be generated from expressions that contain the discontinuous Galerkin operators introduced in UFL. In order to maintain computational efficiency for complex problems, various optimisation strategies for computing the local finite element tensor are implemented in the FFC. The central philosophy of the optimisation strategies is to manipulate the representation in such a way that the number of operations to compute the local element tensor decreases. As an example, to demonstrate the extensions to the FEniCS framework developed in this work, a strain gradient plasticity model which includes a lifting-type discontinuous Galerkin formulation for the plastic multiplier is presented. It is demonstrated that the model is not suitable for softening problems. On the other hand, the model is able to capture size effects for a hardening problem in a micro-indentation simulation in three dimensions.Structural EngineeringCivil Engineering and Geoscience
Realistic Online Resource Management for Partially Reconfigurable Systems
No full textIn this dissertation, we focus our research on the problems related to efficient configurable resource management for partially reconfigurable systems. FPGA devices are used to build such systems for various application domains with telecommunication and energy efficient high performance computing being two prominent examples. Dynamic management of FPGA hardware resources is an important problem and is the main motivation for this dissertation. Our research starts with investigating an abstract view of configurable resources which represents the essential properties of FPGAs in respect to reconfiguration while leaving out many less important technology details. In this step, a realistic model with adequate complexity is exposed to the configurable resource management algorithms. Next, based on the abstract view, the hardware task's spatial requirements are studied and an efficient online task placement algorithm is proposed. Our placement algorithm dynamically redistributes the reconfigurable resources into blocks with various sizes and outperforms state of the art. In addition, a new model for measuring and analyzing the placement algorithms performance is built. In our next step we take into account also task's temporal requirements and consider holistic online task placement and scheduling. A novel algorithm with support for application specific scheduling heuristics is proposed. In addition, a reuse and partial reuse mechanism is applied to alleviate the single configuration port limitation present in modern systems. After that, a communication model is introduced into the abstract view and the proposed online scheduling algorithm is extended to account the communication paths among data dependent hardware tasks and between tasks and external peripherals. In this step, the complete realistic configurable resource management problem is addressed. Furthermore, mechanisms for hardware reuse and interrupt handling are proposed. The hardware reuse mechanism gives the required hardware support for the reuse and partial reuse mechanisms. The hardware interrupt handling mechanism enables real time applications on reconfigurable systems.Software Computer TechnologyElectrical Engineering, Mathematics and Computer Scienc
Customizable Register Files for Multidimensional SIMD Architectures
No full textProcessor clock frequencies and the related performance improvements recently stagnated due to severe power and thermal dissipation barriers. As a result, the additional transistors provided by new technology generations are turned into more processing elements on a chip and used for their specialization towards power efficiency. For data parallel workloads the Single Instruction Multiple Data (SIMD) accelerators form a good example. SIMD processors, however, are notorious for turning performance programmers into low-level hardware experts. Moreover, legacy programs often require rework to follow (micro)architectural evolutions. This dissertation addresses the problems of SIMD accelerators programmability, code portability and performance efficient data management. The proposed Polymorphic Register File (PRF) provides a simple programming interface, allowing programmers to focus on algorithm optimizations rather than complex data transformations or low-level details. The overall PRF size is fixed, while the actual number, dimensions and sizes of its individual registers can be readjusted at runtime. Once the registers are defined, the microarchitecture takes care of the data management. We base our proposal on a 2D addressable multi-banked parallel storage, simultaneously delivering multiple data elements for a set of predetermined access patterns. For each pattern, we declare a Module Assignment Function (MAF) and a customized addressing function. We propose four MAF sets fully covering practical access patterns and evaluate them in a technology independent way. Next, we study a multi-lane, multi-port design and its HDL implementation. Clock frequencies of 100 to 300 MHz for FPGA and 500 to 900+ MHz for ASIC synthesis strongly indicate our PRF practical usability. For representative matrix computation workloads, single-core experiments suggest that our approach outperforms the Cell SIMD engine by up to three times. Furthermore, the number of executed instructions is reduced by up to three orders of magnitude compared to the Cell scalar core, depending on the vector registers size. Finally, we vectorize a separable 2D convolution algorithm for our PRF to fully avoid strided memory accesses, outperforming a state of the art NVIDIA GPU in throughput for mask sizes of 9 x 9 elements and bigger.Software and Computer TechnologyElectrical Engineering, Mathematics and Computer Scienc
Efficient Runtime Management of Reconfigurable Hardware Resources
No full textRuntime reconfigurable systems built upon devices with partial reconfiguration can provide reduction in overall hardware area, power efficiency, and economic cost in addition to the performance improvements due to better customization. However, the users of such systems have to be able to afford some additional costs compared to hardwired application specific circuits. More precisely reconfigurable devices have higher power consumption, occupy larger silicon area and operate at lower speeds. Higher power consumption requires additional packaging cost, shortens chip lifetimes, requires expensive cooling systems, decreases system reliability and prohibits battery operation. The less efficient usage of silicon real estate is usually compensated by the runtime hardware reconfiguration and functional units relocation. The available configuration data paths, however, have limited bandwidth that introduces overheads that may eclipse the dynamic reconfiguration benefits. In this dissertation, we address three major problems related to hardware resources runtime management: efficient online hardware task scheduling and placement, power consumption reduction and reconfiguration overhead minimization. Since hardware tasks are allocated and deallocated dynamically at runtime, the reconfigurable fabric can suffer of fragmentation. This can lead to the undesirable situation that tasks cannot be allocated even if there would be sufficient free area available. As a result, the overall system performance is degraded. Therefore, efficient hardware management of resources is very important. To manage hardware resources efficiently, we propose novel online hardware task scheduling and placement algorithms on partially reconfigurable devices with higher quality and faster execution compared to related proposals. To cope with the high power consumption in field programmable devices, we propose a novel logic element with lower power consumption compared to current approaches. To reduce runtime overhead, we augment the FPGA configuration circuit architecture and allow faster reconfiguration and relocation compared to current reconfigurable devices.Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Feasibilty Analysis for Hardware Acceleration of Pattern Recognition Algorithms
No full textThis thesis presents a feasibility analysis for hardware acceleration of the pattern recognition algorithms used by the Media Knowledge Engineering department at the Delft University of Technology. The feasibility analysis is conducted on a number of different algorithm classes. The Parzen Window algorithm appeared to be the most suitable option for acceleration when recongurable hardware is considered. The reason for this is that the Parzen Window consists of independent calculations that can be computed in parallel. It can be computed by execution of Custom Configured Hardware Units (CCU) in Field Programmable Gate Arrays (FPGAs). The feasibility analysis presented, gave insight in the question whether it is useful to implement these kind of algorithms in hardware. Our results showed that algorithms that have independent calculations and thus are able to be executed in parallel are strong candidates for hardware implementation, certainly when the design can be executed with integer calculations. Integer calculations reduce the complexity of hardware implementation, require smaller area on the FPGA, reduce the bandwidth of the calculations and can be computed faster than their floating point version. In the future our methodology can be reused for other algorithms that have a parallel structure.Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
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