1,721,076 research outputs found
Throughput Optimization for Area-Constrained Links With Crosstalk Avoidance Methods
No full textThe effect of crosstalk avoidance codes on the throughput of fixed width communication channels is studied. Closed form expressions of the throughput which incorporate the dimensions of the interconnects and the wiring overheads incurred by such techniques are derived for lines under different buffering conditions. These formulae are utilized to optimize the bandwidth of constrained-area parallel buses under different latency and power constraints. Our results are confirmed by the simulations we have performed in Spectre for a UMC CMOS 90-nm technology
Fault-Tolerant Techniques to Minimize the Impact of Crosstalk on Phase Encoded Communication Channels
No full textAn on-chip intermodule self-timed communication system is considered in which symbols are encoded by means of phase difference between transitions of signals on parallel wires. The reliability of such a channel is governed and significantly lowered by capacitive crosstalk effects between adjacent wires. A more robust high-speed phase-encoded channel can be designed by minimizing its vulnerability to crosstalk noise. This paper investigates the impact of crosstalk on phase-encoded transmission channels. A functional fault model is presented to characterize the problem. Two fault-tolerant schemes are introduced which are based on information redundancy techniques and a partial-order coding concept. The area overheads, performance, and fault-tolerant capability of those methods are compared. It is shown that a substantial improvement in the performance can be obtained for four-wire channels when using the fault-tolerant design approach, at the expense of 25 percent of information capacity per symbol
Bandwidth-Centric Optimisation for Area-Constrained Links with Crosstalk Avoidance Methods
No full textThe effect of crosstalk avoidance codes on the throughput of fixed width communication channels is studied. Closed form expressions of the throughput which incorporate the dimensions of the interconnects and the wires overheads by such techniques are derived for lines under different buffering conditions. These formulae are utilised to optimise the bandwidth of fixed width parallel buses under different latency and reliability constraints. Our results are confirmed by the simulations we have performed in Spectre for a UMC CMOS 90 nm technology
Is a single cell sensor possible?
No full textA cell-based implant is a miniaturized sensor that can be placed inside a biological living cell. This device would be able to interrogate and possibly affect biological functions in vivo. This paper explores the requirements of such a system; it also investigates the changes that need to be brought about in both fabrication technologies and design methodologies to make this visionary application a reality
Eliminating synchronization latency using sequenced latching
No full textModern multicore systems have a large number of components operating in different clock domains and communicating through asynchronous interfaces. These interfaces use synchronizer circuits, which guard against metastability failures but introduce latency in processing the asynchronous input. We propose a speculative method that hides synchronization latency by overlapping it with computation cycles. We verify the correctness of our approach through a field programmable gate array implementation and apply it to a number of synthesized benchmarks. Synthesis results reveal that our approach achieves average savings of 135% and 204% in area costs and nearly 100% in power costs compared to two similar speculative technique
Bootstrapped driver and the single-event-upset effect
No full textAs VLSI circuits are progressing in very Deep Submicron (DSM) regime without decreasing chip area, the importance of global interconnects increases but at the cost of performance and power consumption. This work proposes a low power circuit for driving a global interconnect at voltages close to the noise level. In order to address ultra-low power (ULP) design limitations, a novel driver scheme has been configured. This scheme uses a bootstrap circuitry which boosts the driver's ability to drive a long interconnect with an important feedback feature in it. Hence, this approach achieves two objectives: improving performance and mitigating power consumed. Those achievements are essential in designing ULP circuits along with occupying a smaller footprint and being immune to noise, observed in this design as well. These have been verified by comparing the proposed design to the previous and traditional circuits using a simulation tool. Additionally, the boosting based approach has been shown beneficial in mitigating the effects of single-event upsets (SEU), which are known to affect DSM circuits working under low voltages. As a result, the proposed circuit demonstrates a promising solution to address the energy and performance issues related to scaling effects on interconnects along with soft errors that can be caused by neutron particles
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