3,892 research outputs found
Chun qiu Zuo zhuan zhu shu: [60 juan]. v.92
No full text杜氏[預]註 ; 孔頴達疏.綫裝.框17.9 x 12.5 公分, 9行21字, 小字雙行同, 白口, 無魚尾, 左右雙邊, 版心下刻"汲古閣".Xian zhuang.Kuang 17.9 x 12.5 gong fen, 9 hang 21 zi, xiao zi shuang hang tong, bai kou, wu yu wei, zuo you shuang bian, ban xin xia ke"ji gu ge".Du shi [Yu] zhu ; Kong Yingda shu
Fully parallel implementation of timing-error-tolerant LDPC decoders
No full textIn this thesis, the design of fully parallel timing-error-tolerant Low-Density Parity-Check (LDPC) decoders have been investigated. LDPC decoders are employed in numerous communication systems to correct channel-induced transmission errors. The ever increasing data traffic demands require LDPC decoders that are capable of providing high processing throughput and low processing latency, using limited hardware resources and energy consumption. The fully parallel implementation of LDPC decoders is suitable, due to the high throughput and low latency that this affords. However, the task of designing reliable Very Large-Scale Integration (VLSI) systems is becoming increasingly challenging in successive generations of nanoscale fabrication technology. This may be attributed to the occurrence of timing errors, during the processing, which is caused by the increasing susceptibility to IR drop, inductive noise, crosstalk, electrostatic discharges, particle strikes, switching noise and fabrication process variations. Therefore it is necessary to consider the effects of timing errors during the design of LDPC decoders. However, the characterization of the timing error tolerance of LDPC decoders relying on measurements obtained directly from a fabricated Application-Specific Integrated Circuit (ASIC) may not be preferable, owing to the associated risk of wasting all of the invested time, effort and expense, if the ASIC is not able to facilitate the desired outcomes. A novel design flow is therefore proposed in this thesis, which allows the use of simulations at the algorithm level to investigate the decoders' error correction performance, with considerations of the occurrence of timing errors in the hardware architecture level of the design.LDPC decoders employing the optimal Sum-Product Algorithm (SPA) have a very high implementation complexity, which requires the exchange of floating point probabilities between the parity-Check Nodes (CNs) and Variable Nodes (VNs) in their factor graph representation. In order to reduce the complexity, the Log-Sum-Product Algorithm(Log-SPA) and the Min-Sum Algorithm (MSA) may be employed in the LDPC decoder, which operate on a basis of Log-Likelihood Ratios (LLRs), rather than probabilities. These LLRs can be represented by Fixed-Point (FP) numbers, comprising a number of bits, referred to as the bit width. It is this bit width that proportionally determines both the size of the memory required, as well as the area of the data path and hence the energy consumption imposed. We propose the use of EXtrinsic Information Transfer (EXIT) charts to select the bit widths for the Fixed-point LDPC Decoders (LDPC-FDs), in order to achieve a desirable trade-off between the implementation complexity and the error correction performance. This significantly expedites the LDPC-FD design process, relative to the conventional approach of using trial and error based Bit Error Ratio (BER) simulations. Using the proposed design flow, timing characteristics analysis may be performed on the LDPC-FD, in order to derive an error model of the causes and effects of timing errors. With the aid of the error model, the error correction performance of the LDPC-FD in the presence of timing errors may be characterized. In this way, the parametrization of the LDPC-FD may be optimized.In Stochastic LDPC Decoders (LDPC-SDs), only a single bit is exchanged between each pair of CNs and VNs in each clock cycle. Over the course of several successive clock cycles, the individual bits that are exchanged between a particular pair of nodes collectively form a Bernoulli sequence, which may replace the LLRs conventionally used in LDPC-FDs. Owing to this, the operations of the CNs and VNs may be implemented using simple logic gates, which grants LDPC-SDs the practical opportunity for fully parallel implementation. As in LDPC-FDs, the proposed design flow may be adopted to guide the investigation of the timing error tolerance of LDPC-SDs, in order to determine their optimal parametrization
Zhong yuan yin yun zuo ci shi fa
No full text(元) 周德淸著 ; 抄坿任中敏[訥]按語 ; 鮑賡生標點 ; 何銘校訂.Caption title: 中原音韻作詞十法.At head of title: 新式標點.(Yuan) Zhou Deqing zhu ; chao fu Ren Zhongmin [na] an yu ; Bao Gengsheng biao dian ; He Ming jiao ding.Caption title: Zhong yuan yin yun zuo ci shi fa.At head of title: Xin shi biao dian
Bianque xin shu shen fang
No full text扁鵲傳 ; 竇材重集 ; 胡珏參論.綫裝.框17.8x12.2公分, 8行20字, 小字雙行同. 白口, 左右雙邊, 單黑魚尾. 版心上鐫題名, 中鐫卷次, 下鐫葉次.分上, 中, 下卷.《神方》末有乾隆乙酉[1765]王琦跋, 言刻書事.《中國中醫古籍總目》05495著錄有乾隆刻本.鈐"莊兆祥印"朱, 白文各一方.Xian zhuang.Kuang 17.8 x 12.2 gong fen, 8 hang 20 zi, xiao zi shuang hang tong. Bai kou, zuo you shuang bian, dan hei yu wei. Ban xin shang juan ti ming, zhong juan juan ci, xia juan ye ci.Fen shang, zhong, xia juan."Shen fang" mo you Qianlong yi you [1765] Wang Qi ba, yan ke shu shi.Detailed notes in vernacular field only.Bian Que zhuan ; Dou Cai chong ji ; Hu Jue can lun.Qian "Zhuang Zhaoxiang yin" zhu, bai wen ge yi fang
Cheng shi yang ge duan ju ji
No full text一場虛驚 : 小型歌劇 / 李建慶, 呂翎編劇 ; 張魯作曲 -- 賣糖姑娘 : 廣場秧歌劇 / 徐步編劇 ; 郭亮作曲 -- 遊京城 : 快板劇 / 李悦之編劇 -- 新態度 : 獨幕小歌劇 / 于雁軍編劇 ; 陳紫作曲.中央戲劇學院創作室編.Zhong yang xi ju xue yuan chuang zuo shi bian.Yi chang xu jing : xiao xing ge ju / Li Jianqing, Lü Ling bian ju ; Zhang Lu zuo qu -- Mai tang gu niang : guang chang yang ge ju / Xu Bu bian ju ; Guo Liang zuo qu -- You jing cheng : kuai ban ju / Li Yuezhi bian ju -- Xin tai du : du mu xiao ge ju / Yu Yanjun bian ju ; Chen Zi zuo qu
Wen zhang zuo fa.
No full text分緖言、作者應有的態度、記敘文、說明文、議論文、小品文6章.夏丏尊, 劉薰宇編.附: 《作文的基本的態度》 , 《論記敘文中作者的地位並評現今小說界的文字》, 《在國文科教授上最近的一信念》c.2 (004495084) incomplete, p. 136- missing.Xia Mianzun, Liu Xunyu bian.Fu: "Zuo wen di ji ben di tai du", "Lun ji xu wen zhong zuo zhe di di wei bin ping xian jin xiao shuo jie di wen zi", "Zai guo wen ke jiao shou shang zui jin di yi xin nian"Fen xu yan, zuo zhe ying you de tai du, ji xu wen, shuo ming wen, yi lun wen, xiao pin wen 6 zhang
Liang jing xin ji
No full text許敬宗等輯. 兩京新記 : [殘1卷] / 韋述撰.Date from preface.殘4卷: 存卷662, 664, 668, 695.框13.1 x 9.1 cm., 9行21字, 黑口, 左右雙邊, 無魚尾, 版心中鐫分冊書名, 下鐫叢書名.Xu Jingzong deng ji. Liang jing xin ji : [can 1 juan] / Wei Shu zhuan.Can 4 juan: cun juan 662, 664, 668, 695.Kuang 13.1 x 9.1 cm., 9 xing 21 zi, hei kou, zuo you shuang bian, wu yu wei, ban xin zhong juan fen ce shu ming, xia juan cong shu ming
Critical success factors for BOT electric power projects in China: thermal power versus wind power
No full textAbstract not availableZhen-Yu Zhao, Jian Zuo, George Zillante, Xin-Wei Wan
Tao kan xin niang xi
No full text著作者余好辨.書名據封面.封面書名前題: 驚世良言.附: 既翁為僧 -- 討看新娘檄.木魚歌文.zhu zuo zhe Yu Haobian.Shu ming ju feng mian.Feng mian shu ming qian ti: Jing shi liang yan.Fu: Ji weng wei seng -- Tao kan xin niang xi.Mu yu ge wen
Inter-layer FEC decoded multi-layer video streaming
No full textLayered video coding creates multiple layers of unequal importance, where the enhancement layers will be affected when the base layer is corrupted. In this treatise, a novel inter-layer FEC scheme is investigated, where the information of the base layer1 is incorporated into the systematic bits of the enhancement layers with the aid of an exclusive-OR operation. When the base layer can be recovered independently, the soft information of the enhancement layers can be deduced by flipping the sign of the check information received. In this case, the protection strength of the enhancement layer is unaffected and no extra protection bits are required. Otherwise, the inter-layer FEC decoding philosophy related to the base layer and the enhancement layer will be activated to assist in decoding the base layer, where the protection of the enhancement layer is additionally exploited to protect the base layer. Data partitioning based experiments show that our proposed scheme outperforms the traditional unequal error protection FEC aided transmission system by about 1.8 dB of channel SNR or 7.7 dB of PSNR at an acceptable complexity
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