6,961 research outputs found
Validation by Measurements of a IC Modeling Approach for SiP Applications
Full text linkThe growing importance of signal integrity (SI) analysis in integrated circuits (ICs), revealed by modern systemin-package methods, is demanding for new models for the IC sub-systems which are both accurate, efficient and extractable by simple measurement procedures. This paper presents the contribution for the establishment of an integrated IC modeling approach whose performance is assessed by direct comparison with the signals measured in laboratory of two distinct memory IC devices. Based on the identification of the main blocks of a typical IC device, the modeling approach consists of a network of system-level sub-models, some of which with already demonstrated accuracy, which simulated the IC interfacing behavior. Emphasis is given to the procedures that were developed to validate by means of laboratory measurements (and not by comparison with circuit-level simulations) the model performance, which is a novel and important aspect that should be considered in the design of IC models that are useful for SI analysi
A 20-bit ±40-mV Range Read-Out IC With 50-nV Offset and 0.04% Gain Error for Bridge Transducers
No full textThis paper presents a 20-b read-out IC with ±40-mV full-scale range that is intended for use with bridge transducers. It consists of a current-feedback instrumentation amplifier (CFIA) followed by a switched-capacitor incremental ΔΣ ADC. The CFIA's offset and 1/ f noise are mitigated by chopping, while its gain accuracy and gain drift are improved by applying dynamic element matching to its input and feedback transconductors. Their mismatch is reduced by a digitally assisted correction loop, which further reduces the CFIA's gain drift. Finally, bulk-biasing and impedance-balancing techniques are used to reduce the common-mode dependency of these transconductors, which would otherwise limit the achievable gain accuracy. The combination of these techniques enables the read-out IC to achieve 140-dB CMRR, a worst-case gain error of 0.04% over a 0-2.5 V common-mode range, a maximum gain drift of 0.7 ppm/°C and an INL of 5 ppm. After applying nested-chopping, the read-out IC achieves 50-nV offset, 6-nV/°C offset drift, a thermal noise floor of 16.2 nV/√Hz and a 0.1-mHz 1/ f noise corner. Implemented in a 0.7-μm CMOS technology, the prototype read-out IC consumes 270 μA from a 5-V supply.Accepted Author ManuscriptElectronic Instrumentatio
The Case Study of Supply Chain Coordination of LCD Driver IC Industry
No full text在供應鏈課題未被廣泛探討之前，所有的競爭基礎多取決於公司內部之交期、成本、品質及服務，但隨著消費者需求變動及科技發展的迅速，只靠公司內部的整合已不足以應付這樣的變動，為了進一步追趕上競爭的腳步，上下游的配合程度便成為另一個重要的競爭基礎。臺灣在今日全球半導體產業供應鏈之中，佔有舉足輕重的角色。然而，過去學術上極少有針對臺灣公司所做的個案分析與其供應鏈狀況的研究與討論。因此本研究擬利用LCD面板之驅動IC供應鏈之資料進行個案研究，瞭解驅動IC產業鏈的狀況及問題。
本研究訪談驅動IC封測代工廠商A公司，蒐集初級與次級資料，根據供應鏈之「物流」、「資訊流」以及「協同整合」進行個案分析與研究。本研究發現驅動IC產業鏈存在以下主要問題：
1. 驅動IC產業中，具有議價能力者為驅動IC設計公司。而市場中許多驅動IC設計公司採取積極管理供應商的態度，使得封測廠商處於被動狀態。
2. 封測廠商與其客戶之間的資訊不透明，造成封測廠商無法掌握真正的需求，加上客戶有超量預定的狀況，使得驅動IC供應鏈中存在著明顯的長鞭效應。
3. 驅動IC供應鏈並未有良好的協同整合，亦無良好的成本分享(Cost-Sharing)模式，處於弱勢之代工廠商必須吸收較高的成本，造成代工廠商不願意大量投資設備來滿足客戶。
根據個案分析，本研究發現封測代工廠商在供應鏈中處於弱勢地位，供應鏈上之成本多半轉移到A公司上，倘若A公司嘗試進行供應鏈相關整合也勢必會面臨到許多問題，因此，本研究認為，A公司應該1. 嘗試合併其他同業廠商。2. 以核心技術開發多元化的產品。3. 加強技術、品質、交期以及服務。藉由以上方法減少對驅動IC設計公司的依賴，並且增加其競爭力，進而加強供應鏈上之議價能力，方能掙脫目前受限於驅動IC設計公司之狀況，開拓其未來。The competence of corporate was normally built by way of delivery, cost, quality and service before the era that supply chain has been far and wide discussed. Nowadays it is difficult to fulfill the variety of consumer’s requirement as well as the fast technology development if count on enterprise internal effort only. The cooperation across supply chain up-stream and down-stream becomes a new competitive advantage to whole parties. Taiwan semiconductor industry plays an important role in the global supply chain, however there was limited case study were investigated. In contrast with the theory of supply chain management, the thesis is focused on the investigation of industrial practice.
The primary and secondary data were collected through interviewed with Au Bumping and Assembly foundry house which is code named “A-company” in the report. The structure of discussion include material flow, information flow and the subject of supply chain coordination. The case study observed the following phenomena in Driver IC supply chain:
1. Driver IC design-house control the majority of resources in the supply chain who has more bargaining power than assembly house.
2. Bullwhip effect is existed due to information asymmetry , batch ordering and over-booking from IC suppliers.
3. The bumping and assembly manufacturing sometimes showed the insufficient agility to support high volume urgent order due to lack of adequate cost-sharing mechanism between IC company and assembly house.
The bumping and assembly house is laid on the inferior bargaining power position compare to the Driver IC company, which lead to the difficult situation for A-company to deal cost sharing request with their customers. In order to get rid of this situation for corporate long-term survive, the following suggestions are recommended to A-company :
1. Expand the economic scale by M&A
2. Diversify the service portfolio to the other relative industry.
3. Reinforce the processing technology, quality, manufacturing turn around time and service.目錄
第一章 緒論 1
1.1 研究動機 1
1.2 研究目的 2
1.3 研究方法 3
1.4 研究流程與架構 3
第二章 文獻探討 5
2.1 推式系統與拉式系統 5
2.2 長鞭效應 8
2.3 供應鏈協同整合 13
第三章 個案介紹 19
3.1 個案公司背景說明 19
3.2 驅動IC產業供應鏈描述 25
3.3 公司狀況 33
第四章 個案分析 49
4.1 物流 49
4.2 資訊流 54
4.3 驅動IC產業之長鞭效應 59
4.4 整體供應鏈之協同整合 62
4.5 管理上之建議 64
4.6小結 68
第五章 結論與建議 69
5.1研究結論 69
5.2研究限制與未來方向 71
參考文獻 7
The Research of Key Success Factors in IC Distributing Industry
No full text電子產業上游零組件領域為晶圓代工、IC設計及邏輯IC、記憶體 IC、被動元件等製造商，在下游終端產品領域則是各式資訊、工業用及消費電子產品、包括電腦產品、手機、顯示器等之製造，電子零組件通路處於電子產業供應鏈中，儘管本身並不一定具備電子零組件或終端產品生產製造的能力，然而卻在產業鏈中佔有重要的地位。IC通路商在產業中扮演著中間者角色：對原廠端而言，其價值在於作為銷售、技術，甚至是庫存的管道；對客戶端而言，除了價格、供貨等考量外，最重要的是能有足夠的技術能力，代客解決設計階段及量產階段的問題，縮短上市時程，迅速開發新產品。
面對3C整合趨勢，IC通路商扮演的角色正在逐漸轉變中。由於新一代的數位消費或通訊商品的生命週期短、上市壓力大，因此製造商必須用更快速的方式取得零件、參考設計（Reference Design），甚至是完整的設計方案，才能儘快將產品推出市面。此時，負責零件銷售的IC通路商也必須為客戶就其所代理的產品提供更完整的解決方案，IC通路商與下游製造商之間的關係，於是不再像從前僅有單純的買賣，而必須涉入客戶的設計過程，甚至必須協助其達到量產目標。
另一方面，隨著「規模經濟」與「產業整合」的效應逐漸發酵，中國大陸以其廉價人力、土地的成本優勢，吸引全球製造業大量外移至中國，大幅壓縮產業獲利。除面對原本就很激烈的同業競爭之外，又必須同時面對上游供應商與下游客戶，及在產業整併的過程所產生的變化，IC通路業者在營運面上將面臨更嚴峻的挑戰。
因此，本研究係針對IC通路產業環境的變化，與經營所面臨的挑戰與課題，歸納出關鍵成功要素，提供產業營運的策略意涵。本研究擬採用個案研究法，經由分析全球及台灣電子零組件通路產業的各項變化、未來發展趨勢，再透過實地訪查通路業者，並輔以公開資訊，進而歸納關鍵成功因素。An electronic component distributor plays an important role in the worldwide electronic supply chain. It is the bridge between principals and customers. For principals, an electronic distributor helps to promote products; for customers, it helps to solve technical problems before mass production and speed up the development of new products.
With the trend of 3C integration, the role of an IC distributor is gradually changing. Not only having the buy-and-sell relationship with its customers, nowadays, IC distributors have to involve more in the design process and offer comprehensive solutions to help customers speed up mass production.
Meanwhile, with the effect of “Economies of Scale”, “Enterprise Integration” and the accelerating manufacturing facilities migration to China, IC distributors are facing thinner profit margin. The scenario undoubtedly makes IC distributors exposed to more tough challenges from its principals and customers.
The research adopts case study method and conducts interviews with three IC distributors with different business models; and concludes the five key success factors in the electronic component distribution industry: the ability in technical support, financial resources control capabilities, information system integration, globally competitive product lines and the sales geographical coverage.第一章 研究緒論...................................... 1
第一節 研究背景.................................... 1
第二節 研究動機與目的.............................. 3
第三節 研究課題.................................... 3
第四節 預期研究貢獻................................ 4
第五節 研究結構與內容.............................. 4
第二章 文獻探討...................................... 6
第一節 通路商的功能與核心價值...................... 6
第二節 通路商的績效評估........................... 15
第三節 關鍵成功因素之分析層面與確認方法........... 19
第四節 台灣半導體通路業之相關研究..................24
第三章 研究設計..................................... 29
第一節 研究架構與流程.............................. 29
第二節 研究方法.................................... 30
第三節 研究變項.................................... 31
第四節 研究對象.................................... 32
第四章 產業分析與個案分析........................... 34
第一節 全球產業規模................................ 34
第二節 產業結構.................................... 36
第三節 產業特性.................................... 38
第四節 產業發展趨勢................................ 39
第五節 產業關鍵成功因素............................ 45
第六節 台灣電子零組件通路產業現況.................. 47
第七節 個案公司分析................................ 54
第八節 個案結論................................. 65
第五章 個案分析與命題發展............................ 66
第一節 技術支援能力............................... 66
第二節 財務資源掌控能力........................... 68
第三節 資訊系統整合應用能力....................... 69
第四節 新產品線開發能力........................... 71
第五節 銷售地區涵蓋度............................. 73
第六章 結論與建議.................................... 76
第一節 研究結論................................... 76
第二節 研究建議................................... 76
第三節 研究限制................................... 80
參考文獻........................................... 8
IC<sub>50</sub> concentrations and maximal inhibition for WU-1 and WU-2 for class I GLUT overexpressing cells.
No full textIC50 concentrations and maximal inhibition for WU-1 and WU-2 for class I GLUT overexpressing cells.</p
A 23-μW Keyword Spotting IC With Ring-Oscillator-Based Time-Domain Feature Extraction
No full textThis article presents the first keyword spotting (KWS) IC that uses a ring-oscillator-based time-domain processing technique for its analog feature extractor (FEx). Its extensive usage of time-encoding schemes allows the analog audio signal to be processed in a fully time-domain manner except for the voltage-to-time conversion stage of the analog front end. Benefiting from fundamental building blocks based on digital logic gates, it offers better technology scalability compared to conventional voltage-domain designs. Fabricated in a 65-nm CMOS process, the prototyped KWS IC occupies 2.03 mm 2 and dissipates 23- power consumption, including analog FEx and digital neural network classifier. The 16-channel time-domain FEx achieves a 54.89-dB dynamic range for 16-ms frame shift size while consuming 9.3 . The measurement result verifies that the proposed IC performs a 12-class KWS task on the Google Speech Command dataset (GSCD) with >86% accuracy and 12.4-ms latency. Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Electronic
Embedding NSM FRP plates for improved IC debonding resistance
No full textThe use of near surface mounted (NSM) fiber reinforced polymer (FRP) strips for strengthening reinforced concrete structures shows great promise as the strains at intermediate crack (IC) debonding are generally much greater than for externally bonded FRP strips. In this research, the NSM technique is taken a step further by embedding the NSM strip, i.e., is by providing cover to the strip. It is shown that embedment can increase the IC debonding resistance by up to three times. Importantly, embedment allows: substantially larger strains at IC debonding and, hence, greater ductility; the use of larger cross sections of FRP plate; and, through providing cover to the NSM, may be the first step in enhancing the fire resistance. In this paper, 20 new pull tests are described from which mathematical expressions are developed for the effect of embedment on both the IC debonding resistance and its associated local bond stress-slip (τ-δ) relationship. © 2008 ASCE.Deric John Oehlers, Matthew Haskett, Chengqing Wu, and Rudolf Seracin
A 15-nW per Sensor Interference-Immune Readout IC for Capacitive Touch Sensors
No full textThis paper presents a readout IC that uses an asynchronous capacitance-to-digital-converter (CDC) to digitize the capacitance of a touch sensor. A power-efficient tracking algorithm ensures that the CDC consumes negligible power consumption in the absence of touch events. To facilitate its use in wake-on-touch applications, the CDC can be periodically triggered by a co-integrated ultra-low-power relaxation oscillator. At a 38-Hz scan rate, the readout IC consumes 15 nW per touch sensor, which is the lowest reported to date.Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Electronic InstrumentationMicroelectronic
3D-IC Technology Characterization and Test Chip Design
Full text linkWith sub-micron silicon processing technology reaching under 30nm, it becomes more difficult for integrated circuits to achieve higher integration through the scaling down of the transistor size. Three-dimensional integrated circuit (3D-IC) technology stacks multiple dies together and connects them using through-silicon vias (TSVs). This is a low cost and highly efficient way to increase integration. TSVs and stacked dies are two major features of the 3D-IC technology. However, the stacked structures using TSV interconnects induce concerns in reliability such as TSV strain effect, heat problem, and TSV coupling at high frequency, etc. The reliability concerns need to be carefully addressed before 3D-IC technologies can be widely adopted by the industry. Many studies have been carried out in this field, but there has not been much significant work done for testing electrical, mechanical and thermal issues of the 3D-IC technology simultaneously on a single test chip. In this work, a test chip including various test structures was designed to study and analyze these issues in a 3D-IC technology. An accurate resistance and capacitance (RC) model of the TSV for low frequency design was developed, high frequency electrical performance of the TSVs was characterized, coupling between TSVs was modeled, and the stress effect and the heat dissipation method were analyzed in the 3D-IC technology. The TSV model could be added to the design kit for future 3D-IC design and other results could be used to improve the reliability of 3D-IC designs and optimize the performance
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