1,078,084 research outputs found
A Novel Echo Cancellation Algorithm and Architecture Based on Multi-Path Adaptive Interpolated FIR Filter
No full text
Soft-Threshold-Based MultiLayer Decision Feedback Equalizer (STM-DFE) Algorithm and VLSI Architecture
No full text
A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes
No full textA unified design framework for vector rotational CORDIC family based on angle quantization process
No full textA Unified View for Vector Rotational CORDIC Algorithms and Architectures Based on Angle Quantization Approach
No full textVector rotation is the key operation employed extensively
in many digital signal processing applications. In this paper,
we introduce a new design concept called Angle Quantization (AQ).
It can be used as a design index for vector rotational operation,
where the rotational angle is known in advance. Based on the AQ
process, we establish a unified design framework for cost-effective
low-latency rotational algorithms and architectures. Several
existing works, such as conventional COordinate Rotational
DIgital Computer (CORDIC), AR-CORDIC, MVR-CORDIC, and
EEAS-based CORDIC, can be fitted into the design framework,
forming a Vector Rotational CORDIC Family. Moreover, we address
four searching algorithms to solve the optimization problem
encountered in the proposed vector rotational CORDIC family.
The corresponding scaling operations of the CORDIC family are
also discussed. Based on the new design framework, we can realize
high-speed/low-complexity rotational VLSI circuits, whereas
without degrading the precision performance in fixed-point
implementations
Fast Convergent Pipelined Adaptive DFE Architecture Using Post-Cursor Processing Filter Technique
No full textMulti-Symbol-Sliced Dynamically Reconfigurable Reed–Solomon Decoder Design Based on Unified Finite-Field Processing Element
No full text- …
