370 research outputs found
A UWB CMOS 0.13μm low-noise amplifier with dual loop negative feedback
No full textA Low-Noise Amplifier for ultra wide band (UWB) applications is presented. The use of a dual-loop negative feedback topology is advantageous, since it allows to achieve both impedance matching and a very low noise figure, and saves a lot of chip area as no bulky inductors are needed. A nullor and a resistive feedback network are employed, and the values of the feedback elements involved are defined in order to fulfill the noise-figure, input impedance and power-gain requirements for an UWB receiver. To ensure circuit stability, frequency compensation is done by means of a phantom zero and the addition of a transistor connected between input and output, thus realizing a multipath structure. The design targets UMC 0.13μm CMOS IC technology and operation from a 1.2-volt supply. From circuit simulations, the power gain of the LNA amounts to 17dB, and the bandwidth spans up to 12GHz. S11 is below -10dB up to 10GHz and the noise figure is below 3dB up to 8GHz, and below 4dB@10GHz. The power consumption equals 14mA. Compared to competitive solutions, using resonating load stages or LC ladder networks, this chip will be much smaller and cheaper; it will use standard CMOS technology, and achieve very low noise, high gain and wide band matching at reasonable power consumption. ©2008 IEEE
Analysis and Design of Power Supply Circuits for RF Oscillators
No full textThis article presents guidelines for designing the power supply blocks of RF oscillators. To preserve their spectral purity, the requirements on the noise and ripple of the supply voltage are firstly evaluated based on the oscillator supply pushing factor and the oscillator Figure-of-Merit (FOM). Those specifications are then employed to design and estimate the power efficiency of an analog low-dropout regulator (LDO) and a switched-capacitor DC-DC converter. As a proof of concept, a 2:1 or 3:2 switched-capacitor DC-DC converter is implemented and directly connected to our previously published 4.9-5.5 GHz LC oscillator. The converter provides a 1V supply voltage with a noise ≤0.9nV/√Hz at 1MHz and does not affect the inherent phase noise of the oscillator. The ripple amplitude of the converter is 30mV while its effect is suppressed by the spur reduction block embedded in the oscillator.Bio-ElectronicsElectronic InstrumentationElectronic
Spread-Spectrum Modulated Multi-Channel Biosignal Acquisition Using a Shared Analog CMOS Front-End
No full textThe key challenges in designing a multi-channel biosignal acquisition system for an ambulatory or invasive medical application with a high channel count are reducing the power consumption, area consumption and the outgoing wire count. This article proposes a spread-spectrum modulated biosignal acquisition system using a shared amplifier and an analog-to-digital converter (ADC). We propose a design method to optimize a recording system for a given application based on the required SNR performance, number of inputs, and area. The proposed method is tested and validated on real pre-recorded atrial electrograms and achieves an average percentage root-mean-square difference (PRD) performance of 2.65% and 3.02% for sinus rhythm (SR) and atrial fibrillation (AF), respectively by using pseudo-random binary-sequence (PRBS) codes with a code-length of 511, for 16 inputs. We implement a 4-input spread-spectrum analog front-end in a CMOS process to demonstrate the proposed approach. The analog front-end consists of a shared amplifier, a 2nd order ADC sampled at , used for digitization, and an on-chip 7-bit PRBS generator. It achieves a number-of-inputs to outgoing-wire ratio of 4:1 while consuming /input including biasing from a power supply and in area
Safety Module for a High Frequency Arbitrary Waveform Generator
No full textThe goal of the REValUE Project is to design a test device which is able to stimulate nerve tissue with current driven, high frequency stimulation in the range from 1 to 15 kHz and 1 to 10 mA. The test device will be used in research to pudendal nerve blockage. This thesis describes the design process of a safety module for this device. The safety module should guarantee that every stimulation with the device is within the safe stimulation parameters, it should stop any stimulation signal that exceeds 15 mA, 10.5 V or 30 μC/cm . In this thesis a design is proposed that can detect over stimulation. In case of over stimulation, further stimulation is stopped and the stimulated tissue is discharged. Additionally, the module discharges the tissue when the device is shut off.The prototype built during this project is able to stop signals that exceeds 26.7 μC/cm , 15.5 mA and 11 V. Design adjustments to improve the performance of the device are proposed in the discussion section, after which the module will be able to prevent exceeding the safety parameters. The requirement for DC blockage turned out to be an issue in the proposed design. An alternative topology has been thought of, but because of time limits the new design could not be tested. After the improvements proposed in chapter 10, the system should meet all the requirements and guarantee safe stimulation.REValU
Arbitrary Waveform Generator for a High Frequency Arbitrary Waveform Neural Stimulator
No full textThe goal of this Bachelor graduation project is to make an electrical stimulator that can be used to help people empty their urinary bladder. Patients that are unable to relax the urethral sphincter are most commonly treated by mechanically emptying the bladder or by sacral root stimulation where the roots are selectively cut. The stimulator to be made must send a high-frequency signal that cancels the blocking of the urethral sphincter. This method should be able to empty the bladder without the use of mechanical devices or selectively cutting nerves. The whole project is divided into three parts: Control and Interface, Arbitrary Waveform Generator and Safety Module. These parts have been performed by three different subgroups. In this report, the Arbitrary Waveform Generator is discussed. The other parts are explained in the respective reports [1, 2]. The requirements for this waveform are to generate a biphasic pulse with frequencies ranging from 1 to 15 kHz. The amplitude range of this pulse should be adjustable between 0 and 10 mA and the pulse width and interphase delay should be fully adjustable. In order to generate this signal, a power management system was necessary. In addition to the power management system, the LPC1343 microcontroller was chosen to control the system. One of its functions is to control a DAC by communication using the SPI protocol. The DAC can linearly control the output voltages between 0 and the offered reference voltage, in this case 3.3 V by sending 10 bits of data. Using a voltage to current converter, made by the Interface and Control subgroup, the output voltage is converted to a current between 0 and 10 mA [1]. Three additional signals from the microcontroller operate an H-bridge. This is a switching circuit that is able to direct the generated current through a load. Using a timer and four interrupt moments, the three signals are generated that can make a cathodic pulse, anodic pulse and can disconnect the current source. The chosen DAC has a close to ideal behavior. Therefore, the conversion from the microcontroller to the voltage to current converter is very precise. The H-bridge works best at low frequencies. At 1 kHz, around 2% of a total pulse of 127.2 μs is needed to reach 63% of the cathodic or anodic amplitude. At high frequencies, the time increases. At 15 kHz, 24% of a total pulse of 8.4 μs is needed to reach the amplitude.REValU
Structured electronic design of high-pass ΣΔ converters and their application to cardiac signal acquisition
No full textAchieving an accurate sub-Hz high-pass (HP) cutoff frequency and simultaneously a high accuracy of the transfer function is a challenge in the implementation of analog-to-digital converters for biomedical ExG signals. A structured electronic design approach based on state-space forms is proposed to develop HPΣΔ modulators targeting high accuracy of the HP cutoff frequency and good linearity. Intermediate transfer functions are mathematically evaluated to compare the proposed HPΣΔ topologies with respect to dynamic range. Finally, to illustrate the design method, an orthonormal HPΣΔ modulator is designed to be implemented in 0.18 μm technology which achieves a linearity of 12-bits.Accepted author manuscriptBio-Electronic
Control & Interface for a High Frequency Arbitrary Waveform generator
No full textIn the REstore Voiding Urinary rEtention (REValUE) project, a high frequency stimulator is designed that should be able to determine the optimal parameters to block the urethral sphincter. In this report the design of the control, interface, current source and electrode switching circuit of the device is explained – the other parts are explained in the reports of the waveform and safety subgroup [1, 2]. The 2,304 cm3 high frequency stimulator has an adjustable frequency (0-15 kHz with 1 kHz step-size), amplitude (0-10mAwith 0.1mAstepsize), pulse width (0-500 ¹s with 1 ¹s step-size) and interphase delay (0-1000 ¹s with 2 ¹s step-size). Two 4-electrode leads of can be connected in mono- and bipolar configuration. Integration of a Liquid-Crystal Display (LCD) screen with Inter-Integrated Circuit messaging bus (I2C) on the NXP LPC1343 shows the user the settings of the stimulation parameters. The current source is designed based on a cascode current mirror, implemented with PNP transistors, using active feedback to control the current. The topology is based on a discrete component implementation.REValU
High-Pass ΣΔ Converter Design Using a State-Space Approach and Its Application to Cardiac Signal Acquisition
No full textCardiac signal acquisition with high linearity and accuracy of the high-pass cut-off frequency imposes a challenge on the implementation of the analog preprocessing and the analog-to-digital converter. This paper describes a state-space-based methodology for designing high-pass sigma-delta (HP Sigma \Delta topologies with high linearity, targeting high accuracy of the high-pass cut-off frequency. Intermediate functions are evaluated mathematically to compare the proposed HP \Sigma \Delta topologies with respect to dynamic range. A sensitivity performance analysis of the noise transfer function with respect to integrator nonidealities and coefficient variations is also described. Finally, to illustrate the design approach, an orthonormal HP \Sigma \Delta modulator is designed to be implemented in 0.18 \mum CMOS technology, is tested with real prerecorded ECG signals.Accepted author manuscriptBio-Electronic
A Switched Capacitor DC-DC Buck Converter for a Wide Input Voltage Range
No full textIn this paper, a power-efficient multiphase Recursive Switched Capacitor (RSC) converter is presented. Conventionally, RSC converters are used to obtain many different output voltages from a fixed input voltage. Here, the converter provides a fixed output voltage of 1 V at 1 mA from an input voltage ranging from 1.4 V to 4.5 V. It has one programmable stage (2:1 or 3:2) followed by four 2:1 stages. Contrary to most conventional topologies, depending on the input voltage, not all the stages are always deployed. This allows to increase the power efficiency of the whole architecture. The flying capacitance of the non-activated stages is transferred to the activated ones. Hence, for any given input voltage, 100 % of the on-chip capacitance is always used for the conversion. For a general 2:1 topology, an analytical analysis of the power losses is carried out and the impact of the overdrive voltage of the switches on the power efficiency is quantified.A novel gate-driver technique for the switches involved in the conversion is proposed. It ensures an optimal overdrive voltage of the transistor, irrespective of its source and drain potentials. The 16-phase interleaved converter employs a charge recycling technique and uses a total on-chip capacitance of 3 nF.The RSC converter is designed to be implemented in a standard 40 nm CMOS process which offers a capacitor density of approximately 2 nF/mm^2. Circuit simulations over the whole input voltage range show a power efficiency never lower than 54 % with a peak value of 92.7 %.Bio-Electronic
An Ultrasonically Powered and Controlled Ultra-High-Frequency Biphasic Electrical Neurostimulator
No full textThis paper presents the design of a neurostimulator performing biphasic ultra-high-frequency electrical stimulation while being driven from ultrasound energy. Unlike conventional constant current or constant voltage stimulators or state-of-the-art ultra-high-frequency stimulators, the system does not convert the input AC signal into regulated DC for storing power and supplying the elements of the circuits. Instead, it uses the received ultrasonic signal frequency (≥1 MHz) for electrically stimulating the tissue directly, and it achieves biphasic stimulation with external control and without storing extra power. This results in a highly efficient and miniature circuit, which has the potential to be used in bioelectronic medicine for stimulating small peripheral nerves deep inside the body. The operation of the circuit was first simulated in LTSpice using a lumped elements model for the impedance of the piezoelectric receivers and the load. Finally, a prototype was tested in vitro with commercial transducers and platinum-iridium electrodes as load.Accepted author manuscriptBio-Electronic
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