1,721,033 research outputs found
Simultaneous Optimisation of Dynamic Power, Area and Delay in Behavioural Synthesis
No full textConcern over power dissipation coupled with the continuing rise in system size and complexity means that there is a growing need for high-level design tools capable of automatically optimising systems to take into account power dissipation, in addition to the more conventional metrics of area, delay and testability. Current methods for reducing power consumption tend to be ad-hoc: for example, slowing down, or turning off idle parts of the system, or a controlled reduction in power supply. The behavioural synthesis system described in this paper features an integrated incremental power estimation capability, which makes use of activity profiles, generated automatically through simulation of a design on any standard VHDL simulator; accurate circuit-level cell models (generated, again automatically, via Spice simulation); and a comprehensive system power model. This data, along with similar estimators for area and delay, guides the optimisation of a design towards independent, user-specified objectives for final area, delay, clock speed, and energy consumption. In addition, a range of power reducing features are included encompassing: supply voltage scaling, clock gating, input latching, input gating, low-power cells, and pipelined and multicycle units. These are automatically exploited during optimisation as part of the area/delay/power dissipation trade-off process. The resulting system is capable of reducing the estimated energy consumption of several benchmark designs by factors of between 3.5 and 7.0 times. Furthermore, the design exploration capability enables a range of alternative structural implementations to be generated from a single behavioural description, with differing area/delay/power trade-offs
Optimisation in behavioural synthesis using hierarchical expansion: module ripping
No full textDuring behavioural synthesis, an abstract functional description of a system is mapped automatically onto a physical structure. In a competitive setting, this mapping will be highly optimised - the dataflow is re-arranged, units and registers are multiplexed and so on - to deliver a final structure that meets some overall user supplied specification. Ultimately, however, the physical functional units are drawn from some predefined (human designed) library - these may be thought of as the leaf-level modules in the design hierarchy. Design re-use and increasing sophistication of module libraries inevitably leads to leaf modules becoming larger and more complex. As these modules are, by definition, atomic, a synthesis system is unable to capitalise on any internal similarities the leaf modules may possess. This paper describes the design, construction and effects of using a hierarchically defined module library. The set of leaf-level modules made available to the synthesis environment is conventional - add, subtract, multiply and so on - but the optimiser is capable of ?ripping apart? these modules to manipulate their inner structures. Two advantages accrue from this technique: (1) it is possible to optimise behavioural designs far more effectively, with up to a 65% reduction in area, and a 46% reduction in delay reported, and (2) it is possible to build library modules that have tightly controllable internal timing relationships. This is essential when designing systems that communicate externally via low-level protocols, but behavioural synthesis, by its very nature, usually distorts timing information. Using this technique, it is possible to create ?islands of fixed timing? embedded in the synthesised design
A Behavioural VHDL Synthesis System using Data Path Optimisation
No full textMOODS (Multiple Objective Optimisation in Data and control path synthesis) is a synthesis system which provides the ability to automatically optimise a design from a behavioural to a structural VHDL description. This thesis details two sets of enhancements made to the original system to improve the overall quality of the final hardware implementations obtained, and expand the range of the accepted VHDL subset. Whereas the original MOODS considered each functional unit in the target module library to be a purely combinational logic block, the ?expanded modules? developed for this project provide a means of implementing sequential multi-cycle modules. These modules are defined as technology-independent templates, which are inline expanded into the internal design structure during synthesis. This enables inter-module optimisation to occur at the sub-module level, thus affording greater opportunities for unit sharing and module binding. The templates also facilitate the development of specialised interface modules. These enable the use of fixed timing I/O protocols for external interfacing, while maintaining maximum scheduling flexibility within the body of the behaviour. The second set of enhancements includes an improved implementation of behavioural VHDL as input to the system. This expands the previously limited subset to include such elements as signals, wait statements, concurrent processes, and functions and procedures. These are implemented according to the IEEE standard thereby preserving the computational effects of the VHDL simulation model. The final section of work involves the development and construction of an FPGA-based real-time audio-band spectrum analyser, synthesised within the MOODS environment. This design process provides valuable insights into the strengths and weaknesses of both MOODS and behavioural synthesis in general, serving as a firm foundation to guide future development of the system
The MOODS Behavioural Synthesis System
No full textMOODS (Multiple Objective Optimisation in control and Datapath Synthesis) is a behavioural synthesis system developed at the University of Southampton over the last fifteen years. Four out of five of the technical contributions for this session are about MOODS, and so this paper provides a common introduction to do away with unnecessary duplication. This written paper is in two parts; the first supplying an overview to the MOODS system, and providing necessary technical background for the system, and the second (shown as MOODS, The Future in the technical programme) describes the next phase of development of the suite, and provides pointers for the capabilities that we hope to realise in the forthcoming few years
Case Study: Comparing Behavioural with RTL Synthesis in the Development of a Programmable Digital Filter using VHDL
No full textThis paper details a project to develop a simple digital filter on an FPGA, using both RTL synthesis, and a behavioural synthesis tool: MOODS. The aim of the project was to compare and contrast the different approaches and to explore their relative strengths and weaknesses. The language used throughout the project was VHDL. A further goal was to illustrate some of the principal features of the MOODS behavioural synthesis system, and show how an automated tool can address many of the issues in the design industry. The project shows how, although using RTL synthesis can produce a slightly smaller implementation, the behavioural approach provides a substantial reduction in development time, and furthermore, enables the generation of many alternative implementations from a single description
A VHDL Behavioural Synthesis System Featuring Simultaneous Optimisation of Dynamic Power, Area and Delay
No full textPower dissipation has become one of the main concerns of the design industry today. Methods for reducing power consumption tend, however, to be used in an ad-hoc manner. This paper details the incorporation of a power optimisation criterion within the MOODS behavioural synthesis system which features an integrated incremental power estimation capability enabling the system to optimise a design based on independent, user-specified objectives for final area, delay, clock speed, and power consumption. The tool also incorporates a number of architectural features specifically targeted at reducing power which can be included automatically within any given design during synthesis. The resulting system has shown itself to be capable of reducing the energy consumption of a range of benchmark designs by between 3.5 and 7.0 times
A VHDL Behavioural Synthesis System with Floating Point Support
No full textThis paper describes an enhancement to the MOODS (Multiple Objective Optimisation in Data and control path Synthesis) behavioural VHDL synthesis system to support the processing of designs containing floating-point (and complex) arithmetic. In particular, the development of a floating-point module library and a floating-point optimiser capable of making strategic decisions about the high level binding of each floating-point operation in a way that meets the users pre-defined goal. The floating-point modules are based around either iterative generating techniques or lookup tables; either way, the scope of optimisation is considerable, especially when targeting limited architectures such as FPGAs
In-line Test of Synthesised Systems Exploiting Latency Analysis
No full textDuring normal operation, there are periods of time in which units in a digital system (adders, multipliers etc.) are inactive, i.e. are not processing any useful data. These ?latent periods? may be exploited to continually perform sets of unit tests, thus providing a dynamic indication of the healthiness of the system with little or no effect on its performance. This paper details an analysis technique for identifying and quantifying these latent periods by modelling the flow of control through the system as a Markov chain, which takes into account branching and feedback in the controller. The resulting data describes the distribution of latent periods in an entire design, and, given a testing requirement in the form of a minimum number of (latent) cycles required to perform a test, provides a figure for how often and to what extent a particular unit may be tested during normal operation. This analysis is utilised to investigate the impact particular optimisation strategies have on the distribution of latent periods, in a number of synthesised benchmark designs. These results are further developed to demonstrate how a knowledge of the latent period distribution can be used to direct the synthesis process and lead to a substantial improvement in the distribution of latent periods, whilst not over adversely affecting other design aspects, particularly the area
Minimising power dissipation during test application in full scan sequential circuits by primary input freezing
No full textThis paper describes a new technique for minimising power dissipation in full scan sequential circuits during test application. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by reducing spurious transitions during test application. The reduction is achieved by freezing the primary input part of the test vector until the smallest transition count is obtained which leads to lower power dissipation. This paper presents a new algorithm which determines the primary input change time such that maximum saving in transition count is achieved with respect to a given test vector and scan latch order. It is shown how combining the proposed technique with the recently reported scan latch and test vector ordering yields further reductions in power dissipation during test application. Exhaustive experimental results using compact and non compact test sets demonstrate substantial savings in power dissipation using a simulated annealing-based design space exploration. As an example saving of 34% in power dissipation for benchmark circuit s713 is achieved
Hierarchical Module Expansion in a VHDL Behavioural Synthesis System
No full textThis paper describes a technique developed in the MOODS (Multiple Objective Optimisation in Data and control path Synthesis) behavioural VHDL synthesis system whereby functional data-path modules may be dynamically expanded in-situ during the optimisation process, replacing the original ?black box? implementation by its constituent sub-components within the top-level control and data path structure. This enables inter-module optimisation to occur at the sub-module level resulting in substantial area reductions, particularly when targeting restricted device architectures with a limited range of primitive cells, such as FPGAs
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