1,029 research outputs found
High‐frequency trading and financial time‐series prediction with spiking neural networks
No full textA novel new method is introduced - “unsupervised spike learning” - which predicts spikes in price time series instead of price movement and direction. Three rewarding high-frequency trading strategies are developed and backtested by Kang Gao, Wayne Luk, and Stephen Weston
Exploring performance enhancement of event-driven processor networks
No full textEvent-driven processor networks have been proposed as an effective way of exploiting recent advances in field-programmable technology. This paper explores an approach to enhancing the performance of event-driven processor networks for specific applications: Attaching to the processor network accelerators with custom-designed logic. We present a design flow of this approach, and apply the flow to a heatplate application.</p
Neuromorphic design using reward-based STDP learning on event-based reconfigurable cluster architecture
No full textNeuromorphic computing systems simulate spiking neural networks that are used for research into how biological neural networks function, as well as for applied engineering such as robotics, pattern recognition, and machine learning. In this paper, we present a neuromorphic system based on an asynchronous event-based hardware platform. We represent three algorithms for implementing spiking networks on our asynchronous hardware platform. We also discuss different trade-offs between synchronisation and messaging costs. A reinforcement learning method known as Reward-modulated STDP is presented as an online learning algorithm in the network. We evaluate the system performance in a single box of our designed architecture using 6000 concurrent hardware threads and demonstrate scaling to networks with up to 2 million neurons and 400 million synapses. The performance of our architecture is also compared to existing neuromorphic platforms, showing a 20 times speed-up over the Brian simulator on an x86 machine, and a 16 times speed-up over a 48-chip SpiNNaker node
Tele-operated climbing and mobile service robots for remote inspection and maintenance in nuclear industry
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[[alternative]]Totality,reification and social being──Georg Luk?cs’thought of Marxism philosophy and its implications on philosophy of radical adult education
No full text[[abstract]]The purpose of the study is to analyze and interpret the historical background and developmental context of Totality, Reification（Alienation）theory, Ontology about the social being in Luk?cs’ Marxism philosophy, and illuminating its implications and suggestions on radical adult education. In order to accomplish those purposes, the study adopts content analysis, historical hermeneutics, and critical hermeneutics.
Furthermore, before embarking upon Luk?cs’ Marxism philosophy, the researcher will, first of all, attempt to illustrate Luk?cs’ lifetime and development of thought. In addition, the researcher will focus on the on the exploration, Totality, reification theory of Young Luk?cs and the Ontology about social being of Old Luk?cs. In the end, the researcher will illuminate Luk?cs’thought of Marxism philosophy, and inquire its implications on the philosophy of radical adult education.
Accelerating Large-Scale Graph Processing with FPGAs: Lesson Learned and Future Directions
No full textProcessing graphs on a large scale presents a range of difficulties, including irregular memory access patterns, device memory limitations, and the need for effective partitioning in distributed systems, all of which can lead to performance problems on traditional architectures such as CPUs and GPUs. To address these challenges, recent research emphasizes the use of Field-Programmable Gate Arrays (FPGAs) within distributed frameworks, harnessing the power of FPGAs in a distributed environment for accelerated graph processing. This paper examines the effectiveness of a multi-FPGA distributed architecture in combination with a partitioning system to improve data locality and reduce inter-partition communication. Utilizing Hadoop at a higher level, the framework maps the graph to the hardware, efficiently distributing pre-processed data to FPGAs. The FPGA processing engine, integrated into a cluster framework, optimizes data transfers, using offline partitioning for large-scale graph distribution. A first evaluation of the framework is based on the popular PageRank algorithm, which assigns a value to each node in a graph based on its importance. In the realm of large-scale graphs, the single FPGA solution outperformed the GPU solution that were restricted by memory capacity and surpassing CPU speedup by 26x compared to 12x. Moreover, when a single FPGA device was limited due to the size of the graph, our performance model showed that a distributed system with multiple FPGAs could increase performance by around 12x. This highlights the effectiveness of our solution for handling large datasets that surpass on-chip memory restrictions.Quantum Circuit Architectures and Technolog
A domain specific approach to high performance heterogeneous computing
No full textUsers of heterogeneous computing systems face two problems: first, in understanding the trade-off relationships between the observable characteristics of their applications, such as latency and quality of the result, and second, how to exploit knowledge of these characteristics to allocate work to distributed computing platforms efficiently. A domain specific approach addresses both of these problems. By considering a subset of operations or functions, models of the observable characteristics or domain metrics may be formulated in advance, and populated at run-time for task instances. These metric models can then be used to express the allocation of work as a constrained integer program. These claims are illustrated using the domain of derivatives pricing in computational finance, with the domain metrics of workload latency and pricing accuracy. For a large, varied workload of 128 Black-Scholes and Heston model-based option pricing tasks, running upon a diverse array of 16 Multicore CPUs, GPUs and FPGAs platforms, predictions made by models of both the makespan and accuracy are generally within 10 percent of the run-time performance. When these models are used as inputs to machine learning and MILP-based workload allocation approaches, a latency improvement of up to 24 and 270 times over the heuristic approach is seen
Distributed large-scale graph processing on FPGAs
No full textAbstract Processing large-scale graphs is challenging due to the nature of the computation that causes irregular memory access patterns. Managing such irregular accesses may cause significant performance degradation on both CPUs and GPUs. Thus, recent research trends propose graph processing acceleration with Field-Programmable Gate Arrays (FPGA). FPGAs are programmable hardware devices that can be fully customised to perform specific tasks in a highly parallel and efficient manner. However, FPGAs have a limited amount of on-chip memory that cannot fit the entire graph. Due to the limited device memory size, data needs to be repeatedly transferred to and from the FPGA on-chip memory, which makes data transfer time dominate over the computation time. A possible way to overcome the FPGA accelerators’ resource limitation is to engage a multi-FPGA distributed architecture and use an efficient partitioning scheme. Such a scheme aims to increase data locality and minimise communication between different partitions. This work proposes an FPGA processing engine that overlaps, hides and customises all data transfers so that the FPGA accelerator is fully utilised. This engine is integrated into a framework for using FPGA clusters and is able to use an offline partitioning method to facilitate the distribution of large-scale graphs. The proposed framework uses Hadoop at a higher level to map a graph to the underlying hardware platform. The higher layer of computation is responsible for gathering the blocks of data that have been pre-processed and stored on the host’s file system and distribute to a lower layer of computation made of FPGAs. We show how graph partitioning combined with an FPGA architecture will lead to high performance, even when the graph has Millions of vertices and Billions of edges. In the case of the PageRank algorithm, widely used for ranking the importance of nodes in a graph, compared to state-of-the-art CPU and GPU solutions, our implementation is the fastest, achieving a speedup of 13 compared to 8 and 3 respectively. Moreover, in the case of the large-scale graphs, the GPU solution fails due to memory limitations while the CPU solution achieves a speedup of 12 compared to the 26x achieved by our FPGA solution. Other state-of-the-art FPGA solutions are 28 times slower than our proposed solution. When the size of a graph limits the performance of a single FPGA device, our performance model shows that using multi-FPGAs in a distributed system can further improve the performance by about 12x. This highlights our implementation efficiency for large datasets not fitting in the on-chip memory of a hardware device
Accelerating Large-Scale Graph Processing with FPGAs Lesson Learned and Future Directions
No full textProcessing graphs on a large scale presents a range of difficulties, including irregular memory access
patterns, device memory limitations, and the need for effective partitioning in distributed systems,
all of which can lead to performance problems on traditional architectures such as CPUs and
GPUs. To address these challenges, recent research emphasizes the use of Field-Programmable Gate
Arrays (FPGAs) within distributed frameworks, harnessing the power of FPGAs in a distributed
environment for accelerated graph processing. This paper examines the effectiveness of a multi-FPGA
distributed architecture in combination with a partitioning system to improve data locality and
reduce inter-partition communication. Utilizing Hadoop at a higher level, the framework maps the
graph to the hardware, efficiently distributing pre-processed data to FPGAs. The FPGA processing
engine, integrated into a cluster framework, optimizes data transfers, using offline partitioning for
large-scale graph distribution. A first evaluation of the framework is based on the popular PageRank
algorithm, which assigns a value to each node in a graph based on its importance. In the realm of
large-scale graphs, the single FPGA solution outperformed the GPU solution that were restricted
by memory capacity and surpassing CPU speedup by 26x compared to 12x. Moreover, when a
single FPGA device was limited due to the size of the graph, our performance model showed that a
distributed system with multiple FPGAs could increase performance by around 12x. This highlights
the effectiveness of our solution for handling large datasets that surpass on-chip memory restrictions
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