1,720,984 research outputs found
Reconfigurable Accelerators Design Methods for High Reliability Space Applications
Get PDFL'abstract è presente nell'allegato / the abstract is in the attachmen
Hardware-Aware Software-Based Fault Injection Platform for DNN Accelerators
Get PDFEnsuring reliable execution of Deep Neural Networks (DNNs) is crucial for safety-critical applications. Traditional software-based approaches fail to capture real-world fault scenarios, overlooking accelerator datapath effects. We propose a hardware-aware, software-based fault injection platform that emulates systolic array processing, enabling effective fault propagation analysis without the overhead of time-consuming methods
An Integrated Flow for Predicting Radiation Effects in CubeSat Onboard Electronics
No full textWe introduce a simulation-driven methodology to assess the Single Event Effect (SEE) sensitivity of CubeSat electronics under mission-specific radiation environments. By combining component-level Single Event Upset (SEU) cross-section data with detailed 3D structural shielding models, our approach enables fine-grained estimation of SEE rates. Applied to the RAMSES CubeSat mission, it demonstrates that accounting for 3D analysis reduce predicted SEU rates by over 50× compared to simplified standalone models. This improved precision enhances component selection, informs shielding strategies, and streamlines fault mitigation planning, ultimately supporting cost-effective and reliable mission design
ZOR: Zero Overhead Reliability Strategies for AI Accelerators
Get PDFThis research investigates the crucial integration of Neural Network (NN) models with the architecture of the hardware (HW) accelerator. Unlike existing approaches overlooking this interaction, we emphasize understanding the accelerator Datapath for reliability-focused algorithmic solutions. Focusing on Systolic Arrays Datapath, we theoretically evaluate the fault propagation from the HW layer to the NN. This analysis identifies variations in fault effects linked to various data mapping strategies. Considering the fault propagation model, we propose a novel reliability-oriented mapping strategy to mitigate fault effects based on resource rotation. Validation through HW fault injection demonstrates that an architecture-aware NN implementation reduces the impact of faults by up to 40%. Moreover, experimental results indicate that our proposed solution enhances the NN resilience, resulting in up to a 30% reduction in the error rate. Most importantly, these enhancements are attained without introducing performance or hardware overhead
A Comprehensive Analysis of Transient Errors on Systolic Arrays
Get PDFIn recent years, the growth of interest in adopting deep neural network techniques across various domains led to new architectures for supporting the required computational effort. Tensor Processing Units (TPUs), which are based on a systolic array matrix multiplication unit (MMU), became widely popular thanks to their specific structure suitable for Artificial Intelligence. This work investigates Single Event Transient (SET) effects on TPU’s MMU. The analysis demonstrates the impact of SETs on the functionality of MMU when executing digital image processing filtering. The experimental results identify the static and dynamic SET sensitivity of TPU and depict meaningful information on the data dependency of the filters’ kernel values
REMPRO: Reconfigurable Modular Processor
No full textIn space applications, the electronic systems that drive mission critical operations face unique challenges due to harsh environments characterized by temperature variations and cosmic radiation. The reliability and resilience of electronic systems become paramount in ensuring the success of space missions, where the slightest hardware failure can have profound consequences. To address these challenges, this paper introduces REMPRO, a robust processing system designed specifically for space applications. REMPRO's architecture embodies modularity at both the system and device levels, utilizing multiple chained Field-Programmable Gate Arrays (FPGAs), each equipped with a triple modular redundancy (TMR) processor to enhance reliability and fault tolerance. The system is distinguished by having only one active device at a time and the ability to reconfigure autonomously in case of faults, transferring the current state to the subsequent
processor to ensure continuity in mission execution and consequently, enhance overall system availability
Cutting-Edge Strategies for Radiation Effect Estimation on Asteroids Space Mission
Get PDFAssessing the reliability of electronic devices in space is crucial, yet current methodologies often lack realism in reflecting actual mission scenarios. State-of-the-art approaches for Total Ionizing Dose (TID) and Single Event Effects (SEE) estimation face limitations in accurately capturing trajectory-dependent radiation exposure and technology-specific device sensitivity. To address these challenges, we propose advanced methodologies that enhance radiation risk assessment through machine learning and empirical data integration.
Our ML-based TID estimation tool predicts radiation dose based on interplanetary trajectory, mission duration, and shielding thickness. Polynomial regression models, trained on a SPENVIS-generated dataset, enable precise dose estimation by discretizing trajectories and selecting the appropriate model for each segment. Additionally, SEE sensitivity is evaluated using cross-section data from publicly available radiation test databases, combined with particle flux estimates from radiation environment toolS, ensuring technology-aware predictions.
Applied to the Zodiac Pioneer mission feasibility study, our approach provides a comprehensive and efficient radiation environment analysis, surpassing traditional methods in both accuracy and automation
RunSAFER: A Novel Runtime Fault Detection Approach for Systolic Array Accelerators
Get PDFIn this study, we introduce a new runtime fault detection technique for systolic array accelerators oriented to neural network applications. The method exploits the functional path of the systolic array to compute and process checksum values during the execution of the current application instructions flow and integrates self-testing capabilities within the systolic array Instruction Set Architecture. The proposed technique does not require additional hardware self-testing modules, and the test pattern penalty is limited to 3 clock cycles independent of the size of the systolic array. Experimental analysis performed with fault injection campaigns demonstrates full fault detection capabilities of stuck-at faults with an average computing overhead 4 times lower than state-of-the-art solutions. Additionally, our approach exhibits diminished hardware overhead in contrast to conventional techniques
Failure rate analysis of radiation tolerant design techniques on SRAM-based FPGAs
Get PDFSpace applications using SRAM-based FPGA devices demand an accurate evaluation of high-energy radiation particle effects on the design functionality even when mitigation techniques are adopted. In this work, we evaluated the failure rate of different layout solutions of redundancy-based radiation tolerant design. Experimental results achieved thanks to fault injection campaigns and proton radiation tests on different radiation tolerant design implementations demonstrate that an isolation-based redundancy layout provides more than one order of magnitude radiation tolerance capabilities than a commercial solution
Layout-oriented Radiation Effects Mitigation in RISC-V Soft Processor
Get PDFLast decade, the RISC-V soft processor has become popular due to the benefits such as transparency and availability of hardware implementations on reconfigurable devices such as SRAM-based FPGAs. However, these devices are highly sensitive to high-energy particles. For this reason, we propose an implementation methodology that ranges from the hardening method applied at the Register Transfer Level (RTL) to the optimization of layout techniques acting on the place & route of the design. As a case study, the TMR-hardened Arithmetic Logic Unit (ALU) of the RISC-V soft processor implementation was taken and its reliability under different design layouts has been analyzed using fault injection campaigns. Experimental results show that the design reliability can be drastically improved by applying ad hoc layout customization and coupling users’ routing and placement constraints
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