1,721,150 research outputs found
Models and parameters for crosstalk simulation
No full textThis chapter illustrates a simplified model for analysis of crosstalk effects in deep submicron CMOS technologies. Most parameters for parasitic element values can be easily obtained by technology information contained in the physical design rules. However, the substrate bias resistance, which is one of the most important parasitic elements in CMOS technologies with highly-doped substrate with epitaxial layer, is usually neglected in the silicon foundry documentation. The substrate bias resistance value can be obtained either from technology parameters or by experimental measurements on a test structure, and crosstalk effects can be easily estimated through a SPICE-level simulation. The proposed approach has been validated by comparing results with simulations after extracting parasitics with a commercial tool and with experimental measurements on a test chip
Parametric amplifier based dynamic clocked comparator
No full textThe dynamic clocked comparator using a parametric amplifier is proposed and designed using a concept of the charge transfer amplification (CTA). A low gain (5 V/V) reverse discrete-time parametric amplifier (RDTPA) was used as a pre-amplifier stage of the proposed comparator. The level shifter scheme to nullify an input common-mode voltage (VCMI) shows minimal deviation for varying process corners. The complete design including the latch and the RDTPA is designed and fabricated in an STMicroelectronics 32 nm CMOS technology with the supply voltage of 1 V and a sampling frequency of 50 MHz. The fabricated chip results show 7 mV of an input offset voltage, 120 μW of power consumption and 2.4 pJ of energy per comparison
CMOS analog design for wireless communication
No full textThis paper presents an overview of new
problems arising from the ever and ever ubiquitous wireless communication systems. Low cost and high flexibility will be required for future generations of portable
termirials; for these reasons, the market share of CMOS technology is expected to grow quickly. Typical architectures of integrated portable transceivers are described, and solutions in CMOS technology are illustrated, outlining their advantages and drawbacks
A threshold voltage modeling for a spacer-trapping memory cell using Verilog-A
No full textThe threshold voltage of the flash memories varies with respect to the applied voltages at the respective terminal of a memory cell. This paper presents the modeling of the threshold voltage variation for an embedded spacer-trapping memory cell. The effects such as velocity saturation of the transistor and the band-to-band tunneling mechanism have been incorporated in the model. The proposed memory model has been simulated in a standard 0.18 μm CMOS technology. The output results of the proposed model using Verilog-A shows 94.9 ms of erasing time for the programing time of 33.4 ms and for a memory speed of 10 kHz. An increment of 930 mV of the threshold voltage during the programming mode has been recorded
FPGA-based hash circuit synthesis with evolutionary algorithms
No full textAn evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16-bit address space into an 8-bit one. The target technology is FPGA, where the search space of the algorithm is made of the combinational functions computed by cells and of the interconnections among cells. The evolutionary technique has been applied to five different interconnection topologies, specified by neighbourhood graphs. This circuit is readily applicable to the design of set-associative cache memories. Possible use of the evolutionary approach presented in the paper for on-line tuning of the function during cache operation is also discussed
Simulation of mixed-signal circuits for crosstalk evaluation
No full textThis paper presents an approach for simulation of mixed-signal circuits, analyzing possible sources of disturbances in analog-digital integrated systems, such as current pulses drawn from voltage supplies. A closed-form expression of voltage and current in the pull-up and the pull-down of a CMOS logic gate can be derived. A computer program demonstrates the feasibility of the proposed approach. Simulation results of a non-overlapped two-phase clock generator are presented
An analysis of current waveforms in CMOS logic cells for RF mixed circuits
No full textThis paper presents an approach for simulation of mixed-signal CMOS integrated circuits, aiming at estimating crosstalk effects, by identifying possible sources of disturbances in analog-digital integrated systems, such as current pulses drawn from voltage supplies. A simple expression of voltage and current in the pull-up and the pull-down of a CMOS logic gate can be derived. A computer program demonstrates the feasibility of the proposed approach, and a representation of digital switching noise in frequency domain has been derived
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