16 research outputs found
Solar PV parameter estimation using multi-objective optimisation
No full textThe estimation of the electrical model parameters of solar PV, such as light-induced current, diode dark saturation current, thermal voltage, series resistance, and shunt resistance, is indispensable to predict the actual electrical performance of solar photovoltaic (PV) under changing environmental conditions. Therefore, this paper first considers the various methods of parameter estimation of solar PV to highlight their shortfalls. Thereafter, a new parameter estimation method, based on multi-objective optimisation, namely, Non-dominated Sorting Genetic Algorithm-II (NSGA-II), is proposed. Furthermore, to check the effectiveness and accuracy of the proposed method, conventional methods, such as, ‘Newton-Raphson’, ‘Particle Swarm Optimisation, Search Algorithm, was tested on four solar PV modules of polycrystalline and monocrystalline materials. Finally, a solar PV module photowatt PWP201 has been considered and compared with six different state of art methods. The estimated performance indices such as current absolute error matrics, absolute relative power error, mean absolute error, and P-V characteristics curve were compared. The results depict the close proximity of the characteristic curve obtained with the proposed NSGA-II method to the curve obtained by the manufacturer’s datasheet
Parasitic Capacitances of Power Transistors and Their Effects in Power Electronic Systems
No full textPower electronic circuits are often called switching converters because of the use of power semiconductor devices that act as switches to facilitate necessary conversions of electrical energy from one form to another. There are energy losses during this conversion, and the power semiconductor devices are a major contributor to the reduced conversion efficiency. In the case of power transistors, the resistance of the device (commonly referred as “on resistance”) operating as a switch in “on” mode is responsible for the so-called conduction losses, whereas intrinsic parasitic capacitances are responsible for the energy loss during switching between “on” and “off” modes. With the increasing need to reduce the size of switching converters for applications such as battery-operated vehicles, the share of switching losses is increasing due to the use of higher voltages and increased switching frequency. In response to the need for better understanding of the switching losses, this thesis studies the nature and impact of parasitic capacitances on the efficiency of power electronic systems. The devices-under-test are commercial devices of different types i.e. power MOSFET, SJ MOSFET, SiC MOSFETs, and GaN-HEMT.
The thesis is presented in the format of a “thesis by a series of published and unpublished papers” and includes six journal articles/manuscripts as individual chapters. There are four facets of the contributions made by this thesis. The first is a new measurement method for accurate quantification of power losses during turn-on and turn-off intervals. The second is two new equations for accurate calculations of both the energy storage in and a current flow through a voltage-dependent capacitor. The third facet is in terms of providing circuit designers with a simple and transparent SPICE model for GaN˗HEMTs. Finally, a new optimization method is proposed to enable circuit designers to select the best power transistors for specific power electronic systems using two parameters that are readily available in manufacturers’ datasheets.
The contributions from this thesis could help the power-electronic engineers to improve the efficiency of their next-generation systems. This is becoming urgent with the rising concern for environmental protection and energy demand worldwide.Thesis (PhD Doctorate)Doctor of Philosophy (PhD)School of Eng & Built EnvScience, Environment, Engineering and TechnologyFull Tex
Design of a Single-Axis Solar Tracker Using LDRs
No full textTrackers are equipment which are used to get direct sunlight through a uniform orientation according to the position of sun in sky. They are intended to get maximum power through sunlight tracking. Solar technology has been playing a major role in generating electricity. Tremendous research is going in for designing the efficient solar trackers. The initial cost of solar trackers is no doubt high but their running cost and maintenance cost is quite low. Nowadays, solar trackers are becoming beneficial for the grids which are difficult to connect and setup. The smooth operation of solar trackers making them widely used for electricity generation. This paper presents a design of an Op-Amp and relay-based solar tracking system that uses the servo motor and light dependent resistors (LDRs) for the systematic and effective operation.No Full Tex
A Figure of Merit for Selection of the Best Family of SiC Power MOSFETs
No full textThis paper proposes a criterion to select the best family of commercial SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs) that provides the highest quality and reliability. Applying a recently published integrated-charge method, a newly proposed figure of merit is correlated to the density of near-interface traps that degrade the quality and reliability of SiC MOSFETs. The applicability of the proposed figure of merit is experimentally demonstrated with the most widely used and commercially available planar and trench MOSFETs from different manufacturers
A New Parameter Estimation Method of Solar Photovoltaic
No full textThe accuracy in electrical model parameters of solar photovoltaic (PV), such as photon current, the diode dark saturation current, series resistance, shunt resistance, and diode ideality factor, are desirable to predict the real performance characteristics of solar PV under varying environment conditions. First, this paper derives mathematical model of solar PV, in terms of two unknown, namely, series resistance and ideality factor. Then, using combination of analytical method, simulated annealing method, and derived model, a new parameter estimation technique has been proposed. Finally, performance indices, such as PV characteristics curve, relative maximum power error, root mean square deviation, and normalized root mean square deviation are estimated for the various solar PV panels, using proposed and existing methods, to reveal the effectiveness of the proposed method. Also, experimental data have been considered for the validation. Finally, through the comparative analysis of the results, it is revealed that the proposed method offers solar PV characteristics more closer to the real characteristics than the other existing methods.No Full Tex
Quantified density of performance-degrading near-interface traps in SiC MOSFETs
No full textCharacterization of near-interface traps (NITs) in commercial SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) is essential because they adversely impact both performance and reliability by reducing the channel carrier mobility and causing threshold-voltage drift. In this work, we have applied a newly developed integrated-charge technique to measure the density of NITs that are active in the above-threshold region of commercial SiC MOSFETs. The results demonstrate that NITs trap about 10% of the channel electrons for longer than 500 ns.Full Tex
Impact of nitridation on the active near-interface traps in gate oxides on 4H-SiC
No full textIn this paper we have implemented a recently proposed direct-measurement technique to characterize near-interface oxide traps (NITs) in SiC MOS capacitors with gate oxides obtained by four different processes. This measurement technique enables characterization of NITs with energy levels above the bottom of the conduction band, which are active in the accumulation mode of MOS capacitors on N-type SiC and in the strong inversion of N-channel MOSFETs. The measurements revealed that annealing in nitric oxide of thermally grown oxides in dry oxygen removes NITs that are further away from the SiC surface, but it leaves a defect with energy levels located between 0.13 eV and 0.23 eV above the bottom of conduction band. The oxides grown in pure nitric oxide exhibit NITs with energy levels above 0.2 eV. The measurements also show that low-temperature oxide deposition and subsequent annealing in nitric oxide resulted in the lowest density of NITs.No Full Tex
Fast Near-Interface Traps in 4H-SiC MOS Capacitors Measured by an Integrated-Charge Method
No full textOxide traps existing in 4H-SiC MOS capacitors with fast response times that are active in the strong accumulation and depletion regions were characterized by an integrated-charge method. The method is based on the measurement of charging and discharging voltages across MOS capacitors in response to high-frequency voltage pulses. This method can identify traps with response times in the order of hundreds of nanoseconds. The results reveal an increasing density of near-interface traps with energy levels above the bottom of the conduction band, which are the active defects reducing the channel-carrier mobility in 4H-SiC MOSFETs
The Correct Equation for the Current through Voltage-Dependent Capacitors
No full textTwo different equations for the current through voltage-dependent capacitances are used in the literature. One equation is obtained from the time derivative of charge that is considered as capacitance–voltage product: dQ/dt=d[C(V)V]/dt=C(V)[dV/dt]+V[dC(V)/dt]. In the second equation, the term V[dC(V)/dt] does not exist: dQ/dt= C(V)[dV/dt]. This paper clears the ongoing confusion caused by the difference between these two equations. We use the voltage-dependent parasitic capacitance of a commercial Schottky diode in reverse bias mode to test experimentally both equations. The result is that it is incorrect to add the term V[dC(V)/dt] in the first equation with the measured capacitance. We also perform a theoretical analysis, which shows that the differential capacitance, C(V)=dQ/dV, in the correct current equation corresponds to the physical parameters of the diode capacitance.Full Tex
Comparison of the Performance-Degrading Near-Interface Traps in Commercial SiC MOSFETs
No full textThis paper presents a comparison of the density of performance-degrading near-interface traps (NITs) in the most commonly available 1200 V commercial N-channel SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). A recently developed integrated-charge technique was used to measure the density of NITs with energy levels aligned to the conduction band, which degrade MOSFET’s performance by capturing and releasing electrons from the channel biased in the strong-inversion condition. Trench MOSFETs of one manufacturer have lower densities of these NITs in comparison to MOSFETs with the planar gate structure, corresponding to observed higher channel-carrier mobility in trench MOSFETs. Different response-time distributions were also observed, corresponding to different spatial location of the measured NITs.Full Tex
