1,721,041 research outputs found
Calibration of time-interleaved ADCs via Hermitianity-preserving Taylor approximations
No full textA new calibration technique for time-interleaved analog-to-digital converters is proposed, based on Hermitianity-preserving complex Taylor approximations of the frequency response of the correction filters. Calibration is interpreted as approximating these filters with linear combinations of base filters obtained by the proposed Taylor expansion. Known calibration techniques are reinterpreted in this way and compared in terms of accuracy, computational complexity, numerical stability, and convergence time. The new technique is shown to be accurate and to require few hardware resources. The limited number of parameters to estimate enables good performance in fixed-point arithmetic and fast convergence. This is important in background calibration schemes in which parameters need to be estimated in real time
Faster, stabler, and simpler - A recursive-least-squares algorithm exploiting the Frisch-Waugh-Lovell theorem
No full textWe propose a novel recursive least squares (RLS) algorithm that exploits the Frisch-Waugh-Lovell theorem to reduce digital complexity and improve convergence speed and algorithmic stability in fixed-point arithmetic. We tested the new algorithm in the digital background calibration section of a four-channel time-interleaved analog-to-digital converter, obtaining better stability and faster convergence. The digital complexity of the new algorithm in terms of multiplications and divisions is 33% lower asymptotically than that of the conventional Bierman algorithm if the model parameters need not be computed at each update; otherwise, it is the same. Memory requirements are also the same. Because, in calibration, the distance between the ideal and calibrated outputs of the system is to be minimized, the actual value of the model parameters is usually not of interest. Convergence time can be up to 10 or 20 times better in fixed-point arithmetic, and stability for large models is also better in our simulations. In our simulations, when the conventional Bierman RLS algorithm is stable, the steady-state accuracy of the new algorithm is either comparable or better, depending on the simulation setup
A novel 0.5 v MCML D-flip-flop topology exploiting forward body bias threshold lowering
No full textThis brief presents ultra low-voltage CML D-latch and D-Flip-Flop (DFF) topologies in deeply scaled CMOS technologies, able to operate at a supply voltage as low as 0.5 V (no other CML DFFs are able to operate at such a low supply voltage). The topology is based on a modified version of the Folded D-Latch, recently proposed by the authors. In this brief a detailed analysis on the minimum supply voltage allowed by the proposed topologies and a comparison with the one of the other low voltage topologies is also included. Post layout Simulations referring to a commercial 28 nm CMOS process and schematic level simulations adopting 14 nm predictive technology models are provided. They show the heavy advantages of the improved Folded DFF with respect to the state of the art
A high-speed low-voltage phase detector for clock recovery from NRZ data
No full textA novel topology of phase detector (PD) for applications
in clock recovery systems from nonreturn-to–zero data is presented
in this paper. The PD operates directly on the data stream,
without requiring preprocessing, and behaves like a sampling-type
PD, providing a sinusoidal phase characteristic. The triple-tail cell
principle is exploited to obtain a circuit topology suitable to lowvoltage
high-speed applications, with a very simple structure and
thus limited jitter generation. A model is proposed to understand
circuit behavior and optimize its design. The PD has been used in
a clock-and-data recovery circuit for 10-Gb/s optical communications,
and measurements in agreement with SONET specifications
are reported
Simulated power analysis attacks on a DDPL crypto-core without routing constraints
No full textDelay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding power consumption in cryptographic circuits in order to prevent Power Analysis (PA) attacks. Its particular data encoding allows to make the adsorbed current constant for each data input combination, irrespective of capacitive load conditions, which allows to design a PA-resistant circuit without routing constraints. In this work we present a fair comparison between SABL, a well-known state of the art transistor level countermeasure which is sensitive to the capacitive mismatches on the complementary lines and requires a customized routing procedure, and DDPL. After having provided a power model for describing the leakage sources for the above mentioned logics, a simple cryptographic circuit has been designed for both SABL and DDPL, and a CPA attack has been mounted. Simulations results show that when capacitive load unbalances are considered, DDPL strongly outperforms SABL in terms of number of traces required for disclose the secret key. © 2013 IEEE
Secure implementation of TEL-compatible flip-flops using a standard-cell approach
No full textThe Time Enclosed Logic (TEL) is a dual-rail signaling protocol used in the context of cryptographic circuits in order to maintain the time enclosing of information leakage also in the presence of capacitive mismatch. The capacitive mismatch, due to non-perfectly balanced differential routing, provides additional data-dependent leakage that a malicious adversary could use to recover secret information from a hardware implementation. In this work, a novel TEL-compatible standard-cell based flip-flop for cryptographic application is presented. The new flip-flop is intended to be compatible also for FPGA applications. The novel standard-cell architecture has been tested with energy-defined metrics adopting a 4-bit register as case study, implemented in 40nm CMOS process. It has been found that it is able to reduce the data-dependence of the power consumption up to ×0.05 also in the presence of strong mismatch if compared to unprotected CMOS. A comparison with WDDL and MDPL has shown that NED and NSD are remarkably reduced (up to ×30 and ×40 respectively), and their values are independent from the capacitive mismatch in the novel flip-flop architecture
New models for the calibration of four-channel time-interleaved ADCs using filter banks
No full textNew linear models to calibrate four-channel time-interleaved analog-to-digital converters are proposed and investigated. The ideal four-periodic correction filters, which cancel distortions, are computed as a function of the error filters that model the analog transfer function of each channel, including the sampling time. These correction filters are then approximated as a linear combination of base filters and new accurate models with a limited number of free parameters are proposed. Calibration is performed using the recursive least squares algorithm to estimate the coefficients of the linear combination (and the offset term). The resulting algorithms are tested for accuracy, convergence speed, and stability in a fixed-point implementation, and are compared with previously published linear background calibration techniques. The proposed filter bank significantly improves the accuracy/complexity tradeoff with respect to previously published techniques
Dual op amp, LDO regulator with power supply gain suppression for CMOS smart sensors and microsystems
No full textIn CMOS smart sensors and microsystems it can be very convenient to integrate both analog and digital circuits in the same chip; since the supply voltage for high-accuracy, high-precision interfaces should be as immune from disturbances as possible, low drop out regulators are often necessary. Here we show a CMOS, dual op amp, fast, low drop out regulator which allows to diminish the power supply gain by orders of magnitude up to very high frequencies
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