1,721,233 research outputs found
An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores
Full text linkClock generator cores play an increasingly important role in the VU1 design of embedded microprocessors supporting specialized power management modes. We present a fully digital. standardcell-based design of a specialized PLL architecture that can be recompiled on different cell libraries. On a 0.45 μm CMOS implementation. the circuit features a 16 ps jitter, 19.5-to-79 MHz frequency range with a39KHz input. and less than 50 clock cycles wakeup time. © 2001 IEEE
Subsampling models of bandwidth mismatch for time-interleaved converter calibration
No full textBandwidth mismatch is one of the mechanisms that reduce linearity in time-interleaved analog-to-digital converters (TI-ADCs). Models of bandwidth mismatch have been already proposed in the literature: this brief extends them to subsampling signals, validates them against circuit-level simulations, and investigates their effect on linearity in subsampling applications. The effectiveness of two previously published calibration algorithms for the correction of bandwidth mismatch is shown. The proposed models can thus be used to simulate subsampling TI-ADCs and their calibration algorithms
Improved Digital Background Calibration of Time-Interleaved Pipeline A/D Converters
No full textWe propose an algorithm for the digital background calibration of time-interleaved analog-to-digital converters (ADCs), which is capable of accurately calibrating errors due to offset, gain, and timing mismatches, as well as nonlinearities due to errors in the channel ADCs. Calibration is performed in the background without interrupting data conversion, even in the presence of wideband input signals and signals beyond the first Nyquist band. The proposed algorithm improves a previous work by the authors by allowing higher precision, particularly in the case of many interleaved channels and large mismatches. Accuracy improves by 3-8 bits with respect to the previous algorithm and up to 10 bits with respect to the uncalibrated case
Behavioral Modeling for Calibration of Pipeline Analog-To-Digital Converters
No full textIn this paper, a design flow for the design of calibrated pipeline analog-to-digital converters (ADCs), and a framework for their behavioral modeling is presented. The model includes also second order effects such as nonlinearities and linear and nonlinear memory errors, thus allowing fast and accurate simulations of the ADC behavior. In this way, background calibration techniques can be simulated during the design phase, allowing the optimization of ADC performance even under process variations. The design flow can be used to extract information about sensitivity to operating and environmental conditions, post-calibration performance and also design yield, by extracting a database of Monte Carlo realizations of the ADC stages, so that it can be employed to optimize system and circuit design. Simulations using a 0.13-mu m CMOS technology show an accuracy of the model as high as 17 bits
An improved common-mode feedback loop for the differential-difference amplifier
No full textUnconditional stability of the high-gain amplifiers is a mandatory requirement for a reliable steady-state condition of time-discrete systems, especially for all blocks designed to sample-and-hold (S/H) circuits. Compared to differential path, the common-mode feedback loop is often affected by poles and zeros shifting that degrades the large signal response of the amplifiers. This drawback is made worse in some well-known topologies as the difference-differential amplifier (DDA) that shows non-constant transconductance and poor linearity. This work proposes a body-driven positive-feedback frequency compensation technique (BD-PFFC) to improve the linearity for precision DDA-based S/H applications. Theoretical calculations and circuit simulations carried out in a 0.13 mu m process are also given to demonstrate its validity
A comparison among GaAs monolithic processes with respect to the requirements of transimpedance amplifiers using root-locus techniques
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