1,721,321 research outputs found
Radiation effects on the noise parameters of a 0.18um CMOS technology for detector front-end applications
No full text0.13 um CMOS technologies for radiation hardness analog front-end circuits in LHC upgrades
No full textEvaluation of the radiation tolerance of 65 nm CMOS devices for high-density front-end electronics
No full textTotal Ionizing Dose Effects on the Noise Performances of a 0.13 um CMOS Technology
No full textThis paper presents a study of the ionizing radiation tolerance of 0.13 um CMOS transistors, in view of the application to the design of rad-hard analog integrated circuits. Static, signal and noise parameters of the devices were monitored before and after irradiation with 60Co  gamma-rays at a 10 Mrad total ionizing dose. The effects on key parameters such as threshold voltage shift and 1/f noise are studied and compared with the behavior under irradiation of devices in previous CMOS generations
Impact of Lateral Isolation Oxides on Radiation-Induced Noise Degradation in CMOS Technologies in the 100-nm Regime
No full textCMOS MAPS with pixel level sparsification and time stamping capabilities for applications at the ILC
No full textVertically integrated deep N-well CMOS MAPS with sparsification and time stamping capabilities for thin charged particle trackers
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Characterization of a 28 nm CMOS Technology for Analog Applications in High Energy Physics
No full textIn the past few years, the 28 nm CMOS technology has raised interest in the high energy physics community for the design and implementation of readout integrated circuits for high-granularity position-sensitive detectors. This work is focused on the characterization of the 28 nm CMOS node with a particular focus on analog performance. Small-signal characteristics and behavior of the white and 1/f noise components are studied as a function of device polarity, dimensions, and bias conditions to provide guidelines for minimum noise design of front-end electronics. Comparison with data extracted from previous CMOS generations is also presented to assess the performance of the technology node under evaluation
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