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The truth about 2-level transition elimination in bang-bang PAM-4 CDRs
Get PDFReception of 4-level pulse amplitude modulation (PAM-4) requires a clock and data recovery (CDR) circuit, typically implemented by a PLL-like structure. An essential block in such a CDR is the phase detector which should detect whether the recovered clock leads or lags the incoming data edges. In typical implementations an incoming data edge is detected by sensing whether the incoming waveform crosses a data threshold level. However, there is some ambiguity in detecting the incoming data edge because PAM-4 modulation has 3 thresholds. If the waveform crosses multiple threshold levels, the level crossings will occur at different time instants due to the finite rise/fall time of the incoming waveform. In this work, we first analyze qualitatively and quantitatively CDR systems that use one threshold for phase adjustment. Here, eliminating the 2-level transitions decreases the amount of jitter injected by the phase detector. However, the available transitions for phase adjustment are also reduced, which lowers the CDR's robustness. Secondly, for CDR systems using three thresholds, a combination of two techniques: majority voting and elimination of 2-level transitions is investigated. We prove that in this case, the elimination of 2-level transitions is not needed and even gives a worse performance when implemented
Digital PLL-based frequency synthesis: effect of loop filter shape on required DCO frequency resolution
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A digitally controlled threshold adjustment circuit in a 0.13μm SiGe BiCMOS technology for receiving multilevel signals up to 80Gbps
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An 8-phase 10 GHz voltage controlled ring oscillator for 40 Gbit/s BiPON clock-and-data recovery
No full textAnalysis and design of a high power, high gain SiGe BiCMOS output stage for use in a millimeter-wave power amplifier
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