18 research outputs found
Visual Object Recognition by 2D-Color Camera and On-Board Information Processing for Minirobots
No full textChinapirom T, Kaulmann T, Witkowski U, Rückert U. Visual Object Recognition by 2D-Color Camera and On-Board Information Processing for Minirobots. In: Proceedings of the FIRA Robot World Congress. Busan, South Korea; 2004
Ressourceneffiziente Realisierung pulscodierter neuronaler Netze
No full textTim KaulmannPaderborn, Univ., Diss., 200
IAF Neuron Implementation for Mixed-Signal PCNN Hardware
No full textKaulmann T, Lütkemeier S, Rückert U. IAF Neuron Implementation for Mixed-Signal PCNN Hardware. In: Sandoval F, ed. Proceedings of the 9th International Work-Conference on Artificial Neural Networks (IWANN). Lecture notes in computer science. Vol 4507. Berlin, Heidelberg: Springer-Verlag; 2007: 447-454.In this paper, the implementation results of an integrate and fire neuron implemented in a 130 nm process are presented. This publication covers the properties of IAF neurons from calculations on an ideal electrical circuit modeling the soma of an IAF neuron and compares the theoretical results with simulation results from an extracted layout of the implemented neuron
A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation
No full textKaulmann T, Dikmen D, Rückert U. A Digital Framework for Pulse Coded Neural Network Hardware with Bit-Serial Operation. In: Hybrid Intelligent Systems, 2007. HIS 2007. 7th International Conference on. 2007: 302-307.This publication presents a digital framework for build-
ing up pulse coded neural networks with leaky integrate-
and-fire neurons and static synapses as well as dynamic
synapses. The system, including a novel communication in-
frastructure, is mainly focused on ASIC synthesis but also
shows a small footprint on Virtex2(Pro) FPGAs. Its bit-
serial operation has been verified by simulations
A Sub-200mV 32bit ALU with 0.45pJ/instruction in 90nm CMOS
No full textLütkemeier S, Kaulmann T, Rückert U. A Sub-200mV 32bit ALU with 0.45pJ/instruction in 90nm CMOS. In: Semiconductor Conference Dresden. 2009.We have implemented a 32bit ALU operating at voltages from 115mV to 1V on a die area of 0.021mm² in 90nm bulk CMOS. The energy minimum of
0.45pJ/instruction is achieved at a supply voltage of 210mV with the ALUs operating at a clock frequency of 3MHz. A yield of 88.5% can be reported for a supply voltage of 200mV, and 75% for a supply voltage of 120mV
without any body biasing applied. The ALUs have been implemented with an automated design flow and a custom standard cell library, optimized for sub-threshold
operation
Universal mini-robot with micro-processor and reconfigurable hardware
No full textKaulmann T, Witkowski U, Chinapirom T, Rückert U. Universal mini-robot with micro-processor and reconfigurable hardware. In: Proc. of FIRA RoboWorld Conference 2006. 2006: 137-142.In this paper, a novel mini-robot is presented that features several new techniques concerning the chassis of the robot integrating electronic components, the usage of information processing principles and the robot's modularity. The core component for the information processing is a PCB integrating processor running Linux and a closely coupled FPGA offering partial reconfiguration of the FPGA resources for optimizing energy efficiency and computing resources
A Control Approach to a Biophysical Neuron Model
No full textKaulmann T, Löffler A, Rückert U. A Control Approach to a Biophysical Neuron Model. In: Sá JPM de, ed. Proceedings of the International Conference on Artificial Neural Networks. Lecture notes in computer science. Vol 4668. Berlin, Heidelberg: Springer-Verlag; 2007: 529-538.In this paper we present a neuron model based on the description of biophysical mechanisms combined with a regulatory mechanism from control theory. The aim of this work is to provide a neuron model that is capable of describing the main features of biological neurons such as maintaining an equilibrium potential using the NaK-ATPase and the generation of action potentials as well as to provide an estimation of the energy consumption of a single cell in a) quiescent mode (or equilibrium state) and b) firing state, when excited by other neurons. The same mechanism has also been used to model the synaptic excitation used in the simulated system
Impact of shrinking technologies on the activation function of neurons
No full textEickhoff R, Kaulmann T, Rückert U. Impact of shrinking technologies on the activation function of neurons. In: Sá JPM de, ed. Proceedings of the International Conference on Artificial Neural Networks. Lecture notes in computer science. Vol 4668. Berlin, Heidelberg: Springer-Verlag; 2007: 501-510.Artificial neural networks are able to solve a great variety of
different applications, e.g. classification or approximation tasks. To utilize
their advantages in technical systems various hardware realizations do
exist. In this work, the impact of shrinking device sizes on the activation
function of neurons is investigated with respect to area demands, power
consumption and the maximum resolution in their information processing.
Furthermore, analog and digital implementations are compared in
emerging silicon technologies beyond 100 nm feature size
Analog VLSI Implementation of Adaptive Synapses in Pulsed Neural Networks
No full textKaulmann T, Ferber M, Witkowski U, Rückert U. Analog VLSI Implementation of Adaptive Synapses in Pulsed Neural Networks. In: Cabestany J, Prieto A, Sandoval DF, eds. Proceedings of the 8th International Work-Conference on Artificial Neural Networks (IWANN). Lecture notes in computer science. Vol 3512. Berlin, Heidelberg: Springer Berlin Heidelberg; 2005: 455-462.An analog VLSI implementation of adaptive synapses being part of an associative memory realised with pulsed neurons is presented. VLSI implementations of dynamic synapses and pulsed neurons are expected to provide robustness and low energy consumption like observed in the human brain. We have developed a VLSI implementation of synaptic connections for an associative memory which is used in a biological inspired image processing system using pulse coded neural networks. The system consists of different layers for feature extraction to decompose the image in several features. The pulsed associative memory is used for completing or binding features. In this paper, we focus on the dynamics and the analog implementation of adaptive synapses. The discussed circuits were designed in a 130 nm CMOS process
Neural Inspired Architectures for Nanoelectronics
No full textRückert U, Beiu V. Neural Inspired Architectures for Nanoelectronics. In: Sandoval F, ed. Second International Conference on intelligent Computing and Information Systems – ICICIS 2005. Lecture notes in computer science. Vol 4507. Cairo, Egypt: Springer Berlin Heidelberg; 2005: 1-2.Extremely down-scaled field effect transistor, innovative manufacturing of semiconductors, novel material and computing devices have led to rapid changes in the semiconductor industry which now allows more complex systems and more computing power per chip area than several years ago. Albeit these significant improvements novel technology nodes also offer unsolved problems to researchers and challenges to the designers. In this paper, we give a brief overview about actual trends and problems in the semiconductor industry and how the upcoming tasks can be solved by the designers and researchers
