6,440 research outputs found
System and method for a voltage controlled oscillator
No full textIn accordance with an embodiment, an oscillator includes a tank circuit and an oscillator core circuit having a plurality of cross-coupled compound transistors coupled to the tank circuit. Each of the plurality of compound transistors includes a bipolar transistor and a field effect transistor (FET) having a source coupled to a base of the bipolar transistor
A 15.5–39GHz BiCMOS VGA with phase shift compensation for 5G mobile communication transceivers
No full textA BiCMOS VGA for the emerging 5G mobile communication systems operates from 15.5 to 39GHz with a maximum 17 dB gain, features 43 dB gain variation, and, due to the use of compensation circuits, it shows a reduced phase shift variation, namely 3◦ up to 30GHz for a gain variation of 23 dB. The VGA NF is 3.6-9 dB, its IIP3 is -1 dBm, while the power consumption is 104mW
A 12GHz 22dB-gain-control SiGe bipolar VGA with 2° phase shift variation
No full textA 12 GHz VGA is presented that shows a gain control from -9 dB to 13 dB in a linear-in-dB fashion. As the gain is changed, the phase shift over the entire 10 to 14.4GHz bandwidth varies as little as <= 2 degrees due to a compensation circuitry that reduces the input-output phase shift sensitivity to gain variations. The VGA prototypes, implemented in a SiGe bipolar technology, show a noise figure of 5.1 dB, an IIP3 of -3dBm, and a power consumption of 83mW
A X-Band I/Q Upconverter in 65 nm CMOS for High Resolution FMCW Radars
No full textThis work presents a CMOS X-band I/Q upconverter for a FMCW radar system. The use of passive current mixers allows to address the main drawbacks of CMOS technology, namely flicker noise and reduced linearity due to low supply voltage, paving the way to monolithic integration with digital intensive baseband circuitry. Prototypes were built in a 65 nm digital technology, showing a peak output power of -3.4 dBm at 10.6 GHz with a corresponding HD3 lower than -40 dBc and an image rejection greater than 41 dB across the 9.5-12 GHz LO band, while adding negligible phase noise to the output signal. The circuit occupies an area of 0.91 mm(2) and consumes 192 mW
Digital frequency synthesizer with robust injection locked divider
No full textThe disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD
Fast hopping frequency synthesizer
No full textApparatus and systems for synthesizing frequencies for use in a fast hopping wireless communications system. A frequency synthesizer comprises a plurality of oscillators with each oscillator having a first input coupled to a reference clock frequency signal, and a signal selector having a control signal input and a plurality of reference clock inputs with each reference clock input coupled to an output from an oscillator. Each oscillator produces a reference frequency that is a harmonic of a reference clock frequency of the reference clock frequency signal, and the signal selector couples a reference clock input to an output based on a control signal provided by the control signal input
The Future of Canadian Climate Policy — with Marc Lee
No full textMarc Lee is a Senior Economist at the Canadian Centre for Policy Alternatives\u27 BC Office. In addition to tracking federal and provincial budgets and economic trends, Marc has published on a range of topics from poverty and inequality to globalization and international trade to public services and regulation. Marc is the Co-Director of the Climate Justice Project, a research partnership with UBC\u27s School of Community and Regional Planning that examines the links between climate change policies and social justice.Resources:Climate Justice Project: www.policyalternatives.ca/projects/cli…tice-projectMarc Lee\u27s Posts on Policy Note: www.policynote.ca/author/marclee/Canadian Centre for Policy Alternatives: www.policyalternatives.ca/Marc\u27s Twitter: twitter.com/MarcLeeCCPA International Panel on Climate Change, 2021 report: www.ipcc.ch/report/ar6/wg1
SiGe BiCMOS VCO with 27% tuning range for 5G communications
No full textA SiGe BiCMOS VCO with a transformer-coupled varactor operating from 12 to 15.9GHz is presented. The oscillator core features a phase noise as low as -117 dBc/Hz at 1MHz offset from the 14.2GHz carrier while drawing 8mA from the 3.3V supply. The VCO shows a state-of-the-art FoMT of -190 dBc/Hz. The trade-off for the technology selection is described in the introduction. The oscillator is tailored to the communication systems for the upcoming 5G applications. New radios that will operate from 6GHz to as high as 100 GHz may be needed
A quad-core 15GHz BiCMOS VCO with -124dBc/Hz phase noise at 1MHz offset, -189dBc/Hz FOM, and robust to multimode concurrent oscillations
No full textThe relentless development of next-generation communication and radar systems sets increasingly stringent requirements on the spectral purity of local oscillators. Decreasing phase noise is crucial to support efficient modulation formats with large symbol constellations, as well as to enable innovative radar applications, e.g., anti-collision, gesture recognition, and medical imaging. To minimize phase noise, bipolar transistors offer some advantages over ultra-scaled CMOS: higher supply voltage (thus larger oscillation amplitudes), lower 1/f noise, higher-Q passives (due to higher resistivity substrate and, possibly, thicker metals), and higher f T , f max for a given technology node, which results in a cost advantage for a variety of medium-volume applications (e.g., infrastructure transceivers). For a given supply voltage, a tank showing a smaller resistance at resonance yields lower phase noise. As a result, the minimum phase noise achievable by a single voltage-controlled oscillator (VCO) is ultimately bounded by the smaller realizable inductor displaying the highest Q. To achieve significantly lower phase noise levels, bilaterally coupling N oscillators [1-3] is a viable option. However, to fully preserve the 10log(N) phase-noise advantage, while avoiding undesired multi-tone concurrent oscillations, the coupling network must be carefully designed. This work presents a quad-core bipolar VCO achieving phase noise as low as -124dBc/Hz at 1MHz offset from the 15GHz carrier, -189dBc/Hz figure-of-merit (FOM), and 16% tuning range. Insights are given into the design of the resistive network employed to couple the four oscillators, a key element in achieving the reported performance
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