1,721,066 research outputs found
Teaching Task Scheduling as Multivariable Cascade Control
No full textThis paper presents a didactic activity belonging to a long-term project, aimed at complementing the culture of computer engineering students with a solid knowledge of systems and control theory and methods. The use of control to govern and optimise the behaviour of computing systems is felt in the computer engineering community as a necessity. The proposed activity – that refers to task scheduling – responds to this need, guiding the necessary cultural enrichment and avoiding possible errors and misinterpretations, so as to foster a deeper cooperation of the computer and the control communities
Secure and Efficient Design of Block Cipher Implementations on Microcontrollers
No full textThe vast diffusion of microcontrollers has led to their employment in security sensitive contexts, where the need for trusted implementations of cryptographic algorithms is paramount. These architectures are usually endowed with software and occasionally hardware implementation of ciphers, but in both cases, the price envelope is the first figure to be optimised. The strongest threat to microcontroller security has been proven to be represented by side-channel attacks: power consumption analysis and Electromagnetic (EM) emissions analysis being the prime opportunities to retrieve the secret key embedded in the devices via commonly overlooked information leakage. We propose an efficient solution to the problem of compromising EM emissions from an embedded device, showing which are the design space parameters available to the designer, and how to appropriately tune the security margin with respect to the performances, obtaining an order of magnitude improvement over the state-of-the-art solutions
Task Scheduling: a Control-theoretical Viewpoint for a General and Flexible Solution
Full text linkAbstract in UndeterminedThis manuscript presents a new approach to the design of task scheduling algorithms, where system-theoretical methodologies are used throughout. The proposal implies a significant perspective shift with respect to mainstream design practices, but yields large payoffs in terms of simplicity, flexibility, solution uniformity for different problems, and possibility to formally assess the results also in the presence of unpredictable run-time situations. A complete implementation example is illustrated, together with various comparative tests, and a methodological treatise of the matter
A High-Performance, Energy-Efficient Node for a Wide Range of WSN Applications
Full text linkWe present WandStem, a powerful node for WSN applications, ranging from low-power to high-performance ones. WandStem has a powerful 48MHz 32bit CPU with memory protection; thus, it can run untrusted code, to the advantage of security and dependability. It also provides fast current sensing, supporting Coulomb counting and energy profiling. It encompasses hardware timers for packet transmission and reception timestamping allowing accurate time synchronisation and TDMA communication protocols. The node deepsleep current consumption is around 2.4μA; thus supporting long battery lifetime also in ultra-low power application
A Control-based Methodology for Power-performance Optimization in NoCs Exploiting DVFS
Full text linkNetworks-on-Chip (NoCs) are considered a viable solution to fully exploit the computational power of multi- and many-cores, but their non negligible power consumption requires ad hoc power-performance design methodologies. In this perspective, several proposals exploited the possibility to dynamically tune voltage and frequency for the interconnect, taking steps from traditional CPU-based power management solutions. However, the impact of the actuators, i.e. the limited range of frequencies for a PLL (Phase Locked Loop) or the time to increase voltage and frequency for a Dynamic Voltage and Frequency Scaling (DVFS) modules, are often not carefully accounted for, thus overestimating the benefits. This paper presents a control-based methodology for the NoC power-performance optimization exploiting the Dynamic Frequency Scaling (DFS). Both timing and power overheads of the actuators are considered, thanks to an ad hoc simulation framework. Moreover the proposed methodology eventually allows for user and/or OS interactions to change between different high level power-performance modes, i.e. to trigger performance oriented or power saving system behaviors. Experimental validation considered a 16-core architecture comparing our proposal with different settings of threshold-based policies. We achieved a speedup up to 3 for the timing and a reduction up to 33.17% of the power ∗ time product against the best threshold-based policy. Moreover, our best control-based scheme provides an averaged power-performance product improvement of 16.50% and 34.79% against the best and the second considered threshold-based policy setting
FCPP+Miosix: Scaling Aggregate Programming to Embedded Systems
Full text linkAs the density of nodes capable of sensing, computing and actuation increases, it becomes increasingly useful to model an entire network of physical devices as a single, continuous space-time computing machine. The emergent behaviour of the whole software system is then induced by local computations deployed within each node and by the dynamics of the information diffusion. A relevant example of this distribution model is given by aggregate programming and its minimal set of functional constructs used to manipulate distributed data structures evolving over space and time, and resulting in robustness to changes. In this paper, we propose the first implementation of the aggregate computing paradigm targeting microcontrollers, by integrating FCPP, a C++ implementation of the paradigm, with Miosix, a modern operating system for microcontrollers with full C++ support. To the best of the author's knowledge, we are the first to present results on the effectiveness of FCPP in an embedded operating system setting as opposed to a simulation environment, thus considering tight memory and computational constraints and accounting for packet losses due to nonidealities of the radio channel. We implemented and tested on a network of WandStem nodes two benchmark applications: a network connectivity checker for network planning and preventive maintenance, and a decentralised contact tracing application. Additionally, we show that common problems in sensor networks such as neighbour discovery, construction of a graph of the network topology, coarse grain clock synchronisation as well as network monitoring and the collection of statistics (such as memory occupation data) can be easily performed thanks to the expressive semantics of aggregate programming
Feedback-based memory management with active swap-in
No full textAbstract— Memory and swap management is an important
issue in operating systems, owing to the large difference between
RAM and disk access times. This paper presents a memory
management layer, designed along a fully control-theoretical
approach, that decouples the swap-out and swap-in activity
from the events triggered by the applications’ memory access
patterns. A system endowed with this layer can manage memory
on a per-process basis, while at the same time avoiding the
presence of swapped-out pages if RAM memory is available.
Such a tunable active swap-in mechanism thus inherently avoids
temporary RAM over-utilisations to slow down the system for
a period significantly longer than their duration. Simulation
results prove the effectiveness of the proposal, as well as the
viability of its integration with existing memory managers
A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations
Full text linkNetwork-on-Chip (NoC) is a flexible and scalable solution to interconnect multi-cores, with a strong influence on the performance of the whole chip. On-chip network affects also the overall power consumption, thus requiring accurate early-stage estimation and optimization methodologies. In this scenario, the Dynamic Voltage Frequency Scaling (DVFS) technique have been proposed both for CPUs and NoCs. The promise is to be a flexible and scalable way to jointly optimize power-performance, addressing both static and dynamic power sources. Being simulation a de-facto prime solution to explore novel multi-core architectures, a reliable full system analysis requires to integrate in the toolchain accurate timing and power models for the DVFS block and for the resynchronization logic between different Voltage and Frequency Islands (VFIs). In such a way, a more accurate validation of novel optimization methodologies which exploit such actuator is possible, since both architectural and actuator overheads are considered at the same time. This work proposes a complete cycle accurate framework for multi-core design supporting Global Asynchronous Local Synchronous (GALS) NoC design and DVFS actuators for the NoC. Furthermore, static and dynamic frequency assignment is possible with or without the use of the voltage regulator. The proposed framework sits on accurate analytical timing model and SPICE-based power measures, providing accurate estimates of both timing and power overheads of the power control mechanisms
Implementation and evaluation of a control-theoretical scheduler
No full textRecent papers have demonstrated that process schedulers can be designed entirely as feedback controllers—quite novel an approach with respect of the way the control theory is typically applied to computing systems. This work takes a more technological attitude with respect to the methodological ones just quoted. The real- isation of a control-theoretical process scheduler on a kernel written for a microcon- troller is briefly described, and a small sample is presented of the tests performed to assess its correct operation, and to evidence the advantages that the underlying ap- proach yields over classical ones
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