1,720,978 research outputs found
A 16bit 50kHz 177dB-FOMS Calibration-Free Bootstrapping-Free SC Delta-Sigma Modulator IP Block for Low-Power High-Resolution ADCs
No full textThis paper presents a switched-capacitor Delta-Sigma modulator (ΔΣM) IP block for low-power high-resolution ADCs. The ΔΣM IP proposal does not require any circuit calibration neither internal supply bootstrapping. A complete design methodology from architecture to circuit levels with specific optimization of the overall power consumption is included. The presented ΔΣM IP block features a remarkable robustness against both process and temperature variations. For illustrative purposes, two 16-bit 50-kHz IP mapping examples in 1.8-V 180-nm and 1.2-V 65-nm mixed-signal CMOS technologies are presented with post-layout simulation results showing FOMS values around 177 dB
A 72-μW 90-dB wide-range potentiostatic CMOS ∆Σ modulator with flicker noise cancellation for smart electrochemical sensors
No full textThis paper presents a potentiostatic-amperometric Delta-Sigma modulator (∆ΣM) for electrochemical sensors, which reuses the electrode-electrolyte impedance for quantization noise shaping. The proposed ∆ΣM is based on a second-order single-bit CT architecture and it includes a cancellation mechanism of the flicker noise coming from the feedback DAC. Rail-to-rail CMOS basic building blocks for the ∆ΣM circuit implementation are presented with the aim of allowing a wide-range potentiostatic operation. Post-layout simulation results are reported for a complete 72-μW 90-dB smart electrochemical sensor frontend currently being integrated in 0.18-μm 6-metal CMOS technology
A calibration-free 96.6-dB-SNDR non-bootstrapped 1.8-V 7.9-mW delta-sigma modulator with class-AB single-stage switched VMAs
No full textThis paper presents a 96.6-dB-peak-SNDR and 50-kHz-bandwidth switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW. This performance is achieved by the introduction of Class-AB single-stage switched variable-mirror amplifiers (VMAs) combined with an optimized architecture and a 5-phase switched-capacitor scheme. The resulting 1.8-mm2 delta-sigma modulator is integrated in a standard 0.18-μm 1P6M CMOS technology and reaches a Schreier figure of merit of 164.6 dB from experimental SNDR measurements without the need for any clock bootstrapping, analog calibration or digital compensation technique
Class-AB single-stage OpAmp for low-power switched-capacitor circuits
No full textThis paper presents a new family of Class-AB operational amplifier (OpAmp) circuits based on single-stage topologies with nonlinear current amplifiers. The proposed OpAmp architecture is mainly characterized by generating all Class-AB current in the output transistors only, exhibiting very low technology sensitivity and avoiding the need of any internal frequency compensation mechanism. Hence, this family of OpAmps are suitable for low-power switched-capacitor circuits and specifically optimized for switched-OpAmp fast on-off operation and multi-decade load capacitance specifications. A complete OpAmp design example integrated in standard 0.18μm 1P6M CMOS technology is supplied with detailed simulation and experimental results. Compared to MOS-only state-of-art Class-AB OpAmp literature, the proposed architecture returns the highest figure-of-merit value
A 0.8MW 50kHz 94.6DB-SNDR bootstrapping-free SC delta-sigma modulator ADC with flicker noise cancellation
No full textThis paper presents a 0.8-mW 0.2-mm2 9-level second-order single-loop SC Delta-Sigma modulator (ΔΣM) ADC in 1.8-V 0.18-μm CMOS technology for low-power high-resolution sensing applications. The ΔΣM circuit features 94.6-dB peak SNDR in 50-kHz bandwidth and 103.5 dB SFDR up to -1 dBFS input for 2-Vpp differential full scale. The proposed built-in CDS flicker noise cancellation allows a net improvement of 10 dB FOMS. The bootstrapping-free CMOS circuits incorporate variable-mirror Class-AB switched OpAmps and a 10-μW resistor-less flash quantizer. The obtained 172.6-dB FOMS is competitive within the state-of-art high-resolution (SNDR > 90 dB) and general-purpose (bandwidth > 20 kHz) SC ΔΣM ADCs
A 85dB-SNDR 50 kHz bootstrapping-free resistor-less SC Delta-Sigma modulator IP block for PVT-robust low-power ADCs
No full textThis paper presents a switched-capacitor Delta-Sigma modulator (ΔΣM) IP block for low-power high-resolution ADCs. The ΔΣM IP proposal does not require any circuit calibration, internal supply bootstrapping nor resistors. A complete design methodology from architecture to CMOS circuit levels with specific optimization of the overall power consumption is included. The presented ΔΣM IP block features a remarkable robustness against both process and temperature variations. For illustrative purposes, a 50-kHz ΔΣM IP mapping example in 1.8-V 180-nm CMOS technology is presented with experimental SNDRmax>85 dB and FOMS> 160 dB while dissipating 1.4 mW
Variable-Mirror Amplifier: A New Family of Process-Independent Class-AB Single-Stage OTAs for Low-Power SC Circuits
No full textThis paper presents a new family of Class-AB operational transconductance amplifier (OTA) circuits based on single-stage topologies with non-linear current amplifiers. The proposed variable-mirror amplifier (VMA) architecture is mainly characterized by generating all Class-AB current in the output transistors only, by exhibiting very low sensitivity to both technology and temperature deviations, and by avoiding the need for any internal frequency-compensation mechanism. Hence, this family of OTAs is well-suited for low-power switched-capacitor circuits and specifically optimized for switched-OpAmp fast on-off operation and multi-decade load-capacitance specifications. Analytical expressions valid in all regions of operation are presented to minimize VMA settling time in discrete-time circuits. Also, a complete OTA design example integrated in 0.18 μ 1P6M MiM 1.8 V CMOS technology is supplied with detailed simulation and experimental results. Compared to resistor-free state-of-art Class-AB OpAmp and OTA literature, the proposed architecture returns the highest measured figure-of-merit value
Design of a low-power potentiostatic second-order CT delta-sigma ADC for electrochemical sensors
No full textA low-power potentiostatic second-order continuous-time delta-sigma modulator architecture for electrochemical amperometric sensors is presented. The architecture takes advantage of the intrinsic double-layer capacitance of the sensor used as an integrator stage to have a compact and energy efficient conversion of the electrochemical signal. The addition of a second integrator guarantees the real potentiostat operation while introducing new design trade-offs such as stability and resolution. The circuit has been simulated in a standard 0.18 μm CMOS technology. As a proof of concept, a cyclic voltammetry based on real measurements is also presented
Switch-less frequency-domain multiplexing of GFET sensors and low-power CMOS frontend for 1024-channel μECOG
No full textThis paper presents a novel frequency-domain multiplexing scheme of liquid-gate GFET sensors for large-scale μECoG recording. The proposed technique allows the hybrid integration of GFET arrays and read-out ICs. In order to avoid artifacts, the proposal does not employ any switch in the GFET array and it is insensitive to the flicker noise of the CMOS frontend. A modular read-out IC architecture targeting the continuous acquisition of up to 1024 μECoG channels is introduced together with a collection of low-power CMOS circuits for the practical implementation of each building block. A test chip of the proposed system is currently being integrated in 0.18-μm 6-metal CMOS technology
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