4 research outputs found
Optimization of parameters of laser non-linear inclined cutting on stainless steel metal
No full textThe aim of this research is to develop a laser cutting process model that can predict the
relationship between the process input parameters and resultant surface roughness; kerf
width characteristics. The research conduct is based on the Design of Experiment (DOE)
analysis. Response Surface Methodology (RSM) is used in this research, it is one of the
most practical and most effective techniques to develop a process model. Even though
RSM has been used for the optimisation of the laser process, published RSM modelling
work on the application of laser cutting process on cutting material is lacking. This
research investigates laser cutting stainless steel to be best the circumstances laser
cutting using RSM process. The input parameters evaluated are gas pressure, power
supply and cutting speed, the output responses being kerf width, surface roughness. The
laser cutting process is one of the widely used techniques to cut thickness material for
various applications such as fiber, steel wood fabrication. In the area of laser cutting
material,it can be improved drastically with the application of hard cutting. The
application of cut on stainless steel for various machining techniques, such as bevel
linear and bevel non-linear cutting, requires different cut characteristics, these being
highly dependent on the process parameters under which they were formed. To
efficiently optimize and customize the kerf width and surface roughness characteristics,
a machine laser cutting process model using RSM methodology was proposed
SVA checker generator for FPGA-based verification platform
No full textThis paper discusses development of FPGA-based verification platform which consists of System' Verilog assertion (SVA) checker generator to synthesize SVA into Verilog code. We derive a lookup table that consists of SVA operators and their corresponding synthesizable RTL coding. Assertion checker produces single bit-1 which indicates an assertion fails while assertion collection modules must be simple and fast enough to collect the assertion results from assertion checker. In our work, collection module is implemented as arbiter and memory blocks. Case studies have been conducted on 8-bit counter and 8-bit FIFO with 10 assertions and 8 design bugs. Comparison has been done with assertion checker derived from MBAC approach in terms of checker's size. The comparison has showed that the checker size can be reduced further for 17.39%
FPGA-Assisted assertion-based verification platform
No full textIn this paper, field programmable gate array (FPGA)-assisted verification platform is devised to enhance the assertion-based verification methodology to address the issues of high demand of integrated circuit with the advanced features to be delivered to market within tight Time-To-Market. The concept of SystemVerilog Assertion (SVA) checker generator is introduced to translate non-synthesizable verification coding into hardware so-called assertion checker in Verilog. A lookup table, which comprises of SVA operators mapped to their corresponding synthesizable Verilog coding was developed to generate assertion checker, which produces a single bit 1 when the assertion fails. Collection module implemented using a memory block and an arbiter was devised to be simple and fast enough to collect assertion results from the assertion checker. Since assertion checker can produce assertion result at any time, an arbiter is required to act as an interface between assertion checker and collection module. Case studies have been conducted on the proof-of-concept designs, which are the firstin-first-out (FIFO), up-down counter and Context Adaptive Variable Length Coding (CAVLC) to evaluate the effectiveness of the proposed FPGA-assisted verification platform. In the case studies, we have shown that the proposed FPGA-assisted verification platform works correctly. Besides, we also evaluated the method in area utilizations (ALMs). It has been proven that simulation-based verification time can be reduced for as much as 50% for complexity of VLSI design. Thus, implementing assertions using hardware such as FPGA becomes a solution to alleviate issue of long simulation time
FPGA-Assisted Assertion-Based Verification Platform
No full textIn this paper, field programmable gate array (FPGA)-assisted verification platform is devised to enhance the assertion-based verification methodology to address the issues of high demand of integrated circuit with the advanced features to be delivered to market within tight Time-To-Market. The concept of SystemVerilog Assertion (SVA) checker generator is introduced to translate non-synthesizable verification coding into hardware so-called assertion checker in Verilog. A lookup table, which comprises of SVA operators mapped to their corresponding synthesizable Verilog coding was developed to generate assertion checker, which produces a single bit 1 when the assertion fails. Collection module implemented using a memory block and an arbiter was devised to be simple and fast enough to collect assertion results from the assertion checker. Since assertion checker can produce assertion result at any time, an arbiter is required to act as an interface between assertion checker and collection module. Case studies have been conducted on the proof-of-concept designs, which are the firstin-first-out (FIFO), up-down counter and Context Adaptive Variable Length Coding (CAVLC) to evaluate the effectiveness of the proposed FPGA-assisted verification platform. In the case studies, we have shown that the proposed FPGA-assisted verification platform works correctly. Besides, we also evaluated the method in area utilizations (ALMs). It has been proven that simulation-based verification time can be reduced for as much as 50% for complexity of VLSI design. Thus, implementing assertions using hardware such as FPGA becomes a solution to alleviate issue of long simulation time
