1,721,079 research outputs found
An On-line Reliability Emulation Framework
No full textTechnology scaling made reliability a primary concern for integrated circuits. Increased power and temperature exasperate the impact of degradation phenomena and shorten processors lifetime. This issue is particularly dramatic for mobile processors, characterized by variable workload and environmental conditions. Due to the different time scales at which reliability phenomena and computation happens, state-of-theartDRM solutions are evaluated using high-level workload and system models. To enable the design of workload-aware DRM with accurate reliability models, in this work we propose a software framework for virtualizing the processors reliability.Our framework captures the effect of variable workload and environmental conditions and allows to emulate longer degradation in a short time scale. We implement the framework on a realAndroid device and exploit it to enable workload-aware DynamicReliability Management (DRM)
Dynamic variability management in mobile multicore processors under lifetime constraints
No full textVariability is a key issue in modern multiprocessors, resulting in performance and lifetime uncertainty, and high design margins. The margins can be reduced by exposing variability to software and then adapting at runtime. In this work we use sensors to monitor the variable operating conditions and the degradation rate. Based on the sensor data, our variability-aware OS scheduling algorithm assigns the workload to the cores and sets the power/performance tradeoffs to meet the mobile processor's lifetime constraints while adjusting to variability and improving the overall performance. We implement our algorithm in Android OS on a mobile phone and show that it achieves up to 160% performance improvement over the state-of-the-art while meeting the lifetime constraints
A Linux-Governor Based Dynamic Reliability Manager for Android Mobile Devices
Get PDFAbstract—Reliability is a major concern in multiprocessors. Dynamic Reliability Management (DRM) aims at trading off processor performance with lifetime. The state-of-the-art publica-tions study only the theory supported by simulation. This paper presents the first complete software implementation, working on a real hardware, of a low-overhead, Android-compatible workload-aware DRM Governor for mobile multiprocessors. We discuss the design challenges and the run-time overhead involved. We show the effectiveness of our governor in guaranteeing the predefined target lifetime and show that it achieves up to 100 % of lifetime improvement with respect to traditional governors, while providing comparable performance for critical applications. I
Workload and user experience-aware dynamic reliability management in multicore processorsProceedings of the 50th Annual Design Automation Conference on - DAC '13
No full textReliability is a major concern for nanoscale CMOS circuits. Degradation phenomena such as Electromigration, Negative Bias Temperature Instability, Time Dependent Dielectric Breakdown worsen with transistor scaling. Dynamic Reliability Management (DRM) techniques reduce reliability loss at runtime by constraining operating points, but they face the challenge of reducing user experience degradation while meeting a lifetime target. In this work we propose a sensor based hierarchical controller for multicore processor DRM, exploiting the major gap between the time scales of workload variations and reliability loss. We improve performance and user experience by locally relaxing reliability-induced operating point constraints, while meeting them over the large time windows relevant for reliability. With respect to the state-of-the-art, our solution guarantees timely execution of 100% of latency-critical applications, and have a 4% performance improvement over the whole lifetime
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Energy efficient data aggregation in wireless sensor networks
Get PDFWireless sensor networks (WSNs) form a critical interface between physical and digital worlds by converting physical qualities into measurements which can be used for a wide-ranging spectrum of applications. In the past, these WSNs have been application-specific and exposed only to a limited set of users. Going forward, WSNs will no longer be specialized networks. The new emerging IoT will run multiple applications that have diverse delay requirements for generated and received measurements. In this thesis, we propose a power management framework that operates on the sensing platforms which have multiple power managers. For example, sensors are controlled by sensor controller and battery is managed by battery manager in order to minimize the unnecessary energy consumption. The proposed framework integrates these different power management approaches and optimizes their interactions to achieve optimality in terms of energy efficiency. Proposed approach saves 20\% to 60\% of energy consumption compared to the state of art approaches.In addition, we propose an optimal transmission manager that supports multiple applications in single-hop wireless sensor networks. We formulate the problem with Markov decision process model and dynamically adjust transmission instances based on random delay requirements of buffered measurements. Then, we propose a distributed transmission manager that leverages the optimal transmission manager to operate in multi-hop WSNs. We implement both transmission managers in ns3 simulator and compare with other state of the art designs. The results show that the proposed transmission manager consumes on average 148.3% less energy than the state of the art approaches while on average having 14.1% fewer measurements that expire. Lastly, we propose adaptive information dissemination protocol in order to provide information to users in vicinity. Sensors estimate users moving speed and adjust information provision interval in order to save energy. The results show that our proposed approach decrease in power consumption by a factor of 2x to 8x in a single sensor, and 2x to 16x in 10 node sensor network, when compared to the state of art approaches
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Machine Learning in IoT Systems: From Deep Learning to Hyperdimensional Computing
Get PDFWith the emergence of the Internet of Things (IoT), devices are generating massive amounts of data. Running machine learning algorithms on IoT devices poses substantial technical challenges due to their limited resources. The focus of this dissertation is to dramatically increase computing efficiency as well as the learning capability of today’s IoT systems by accelerating existing algorithms in hardware and designing new classes of light-weight machine learning algorithms. Our design makes a modification to storage-class memory to support search-based and vector-based computation in memory. We show how this architecture can be used to accelerate deep neural networks in both training and inference phases, resulting in 303× faster and 48× more energy efficient training as compared to the state-of-the-art GPU.Hardware acceleration alone does not provide all the efficiency and robustness that we need. Therefore, we present Hyperdimensional (HD) computing, an alternative method of learning that implements principles of the functionality in the brain: (i) fast learning, (ii) robustness to noise/error, and (iii) intertwined memory and logic. These features make HD computing a promising solution for today’s embedded devices with limited resources as well as future computing systems in deep nanoscaled technology that have issues of high noise and variability. We exploit emerging technologies to enable processing in-memory which is capable of highly-parallel computation and data movement reduction. Our evaluations show that HD computing provides 39X faster and 56X more energy efficiency as compared to state-of-the-art deep learning accelerator
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Architecting Non-volatile Memory for High Bandwidth Systems
Get PDFHigh-performance processors and emerging deep learning applications require a tremendous amount of data access. Meeting the demands of this bandwidth within the available energy range is a big challenge on current memory systems. Processing-in-Memory (PIM) is a promising solution to address this bandwidth bottleneck by performing a portion of computation inside the memory. Existing state-of-the-art PIM technologies are divided into logic implementation using sensing circuit and cell-based logic-in-memory technology. we present the novel designs that improve performance and energy efficiency in each of these two areas. For the designs using the sensing circuit, we present PIM architecture based on the latch-up effect of thyristors, enabling single-cycle addition (ADD), and significantly improving the performance of multiplication (MUL) This design requires no additional cell array for processing, hence can be an excellent candidate for the storage class memory which has been considered as the main application of memristor-based products. Also, we present the method to carry out multiple bit-lines (BLs) requests under a MUX in parallel, hugely accelerating the PIM applications. Our designs present 16x and 12.7x performance improvement over the state-of-the-art PIM designs, respectively. Considering that cell-based PIM technology is mainly targeted at high-density applications, we present technologies that contribute to energy efficiency and integration. Our UPIM design exploits unipolar switching memristors to offer a sneak current reduction compared to the existing bipolar-based structure and takes advantages of a 3D vertical crossbar array (CBA) structure to increase memory utilization per unit area for high-density applications. As compared to the state-of-the-art PIM design based on the bipolar switching mode, our design achieves 3.1x lower energy consumption and 84% area saving. We also propose a novel design that enables fast and low-overhead computation for very long byte processing by using a multi-block parallelizing method. The proposed design presents 51x energy saving and 16% area saving compared to the state-of-the-art PIM accelerators with a superior cell-efficiency of 45%
Efficient energy management and data recovery in sensor networks using latent variables based tensor factorization
No full textA key factor in a successful sensor network deployment is finding a good balance between maximizing the number of measurements taken (to maintain a good sampling rate) and minimizing the overall energy consumption (to extend the network lifetime). In this work, we present a data-driven statistical model to optimize this tradeoff. Our approach takes advantage of the multivariate nature of the data collected by a heterogeneous sensor network to learn spatio-temporal patterns. These patterns enable us to employ an aggressive duty cycling policy on the individual sensor nodes, thereby reducing the overall energy consumption. Our experiments with the OMNeT++ network simulator using realistic wireless channel conditions, on data collected from two real-world sensor networks, show that we can sample just 20% of the data and can reconstruct the remaining 80% of the data with less than 9% mean error, outperforming similar techniques such is distributed compressive sampling. In addition, energy savings ranging up to 76%, depending on the sampling rate and the hardware configuration of the node
Dynamic power management for portable systems
No full textPortable systems require long battery lifetime while still delivering high performance. Dynamic power management (DPM) policies trade off the performance for the power con-sumption at the system level in portable devices. In this work we present the time-indexed SMDP model (TISMDP) that we use to derive optimal policy for DPM in portable systems. TISMDP model is needed to handle the non-exponential user request interarrival times we observed in practice. We use our policy to control power consumption on three different devices: the SmartBadge portable device [18], the Sony Vaio laptop hard disk and WLAN card. Simula-tion results show large savings for all three devices when using our algorithm. In addition, we measured the power consumption and performance of our algorithm and com-pared it with other DPM algorithms for laptop hard disk and WLAN card. The algorithm based on our TISMDP model has 1.7 times less power consumption as compared to the default Windows timeout policy for the hard disk and three times less power consumption as compared to the default algorithm for the WLAN card. 1
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