198 research outputs found
FPGA-Based IP and SoC Security
No full textIntellectual property (IP) cores in FPGAs are being used widely as these provide high flexibility and efficiency at low cost and low time-to-market. An IP in FPGA is primarily a HDL design or a bitfile for the same. Security aspects have specific issues for the FPGA IP cores. Partial recon gurability of an FPGA has introduced further security holes. A bitfile or a partial bitstream is loaded on an FPGA architecture in encrypted form in order to prevent unauthorized access of the IP. This encryption of the bitfile may be cracked through side-channel attacks. For authentication of a genuine IP vendor and an authorized IP user, their binary signatures may be included in the FPGA bitstream. However, maintaining resilience of the signatures against tampering is a challenge in case of their public verification. Another recent challenge in FPGAs due to hardware Trojans or extraneous circuitry inserted surreptitiously is being combated with parity-based detection techniques. However, it is still hard for the standard FPGA tools to detect Trojan circuits inserted directly in the bitfile cores. In case of a system-on-a-chip (SoC) implemented with FPGAs, the security issues in IP distribution, IP management, and inter-communication are even more complex and challenging. This chapter elaborates the various security techniques adopted in FPGAs, security measures remain as research proposal, along with several alarming security threats open for research
Multi-objective Optimization of Placement and Assignment of TSVs in 3D ICs
No full textThe advent of 3D IC technology facilitates fabrication of large logic circuits on low area yet high performance chips. For a 3D IC, placement followed by assignment of Through-Silicon-Vias (TSV)s is a challenging problem involving various issues like inter-layer wirelength, power density, congestion and variation in surrounding carrier mobility. Each of the existing techniques for placement of TSVs deals only with a subset of these issues. In this paper, we propose an evolutionary approach MO-TSV to handle this multi-objective optimization problem. Although this method has some similarity with the framework of NSGA-II, several variations have been incorporated so that, on exploration of variety of non-dominated solutions the search process converges to a near-optimum solution in reasonable time. Experimental results on ISCAS\u2785 and ISCAS\u2789 benchmarks yield solution quality aswell as convergence times, which are encouraging
SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection
No full textIncreased design complexity, shrinking design cycle, and
low cost—this three-dimensional demand mandates advent
of system-on-chip (SoC) methodology in semiconductor industry.
The key concept of SoC is reuse of the intellectual
property (IP) cores. Reuse of IPs on SoC increases the risk
of misappropriation of IPs due to introduction of several
new attacks and involvement of various parties as adversaries.
Existing literature has huge number of proposals
for IP protection (IPP) techniques to be incorporated in the
IP design flow as well as in the SoC design methodology.
However, these are quite scattered, limited in possibilities in
multithreat environment, and sometimes mutually conflicting.
Existing works need critical survey, proper categorization,
and summarization to focus on the inherent tradeoff,
existing security holes, and new research directions. This
paper discusses the IP-based SoC design flow to highlight
the exact locations and the nature of infringements in the
flow, identifies the adversaries, categorizes these infringements,
and applies strategic analysis on the effectiveness of
the existing IPP techniques for these categories of infringements.
It also clearly highlights recent challenges and new
opportunities in this emerging field of research.</jats:p
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