1,720,994 research outputs found
Universal Processor Architecture for Biomedical Implants: The SiMS Project
No full textHEALTHCARE in the 21st century is changing rapidly. In advanced countries, in particular, healthcare is moving from a public to a more personalized nature. However, the costs of healthcare worldwide are increasing every year. Better use of technology can and should be used to get control of these costs. At the same time, implants have clearly benefitted from the astounding technology-miniaturization trends of late, boasting smaller sizes, lower power consumption and increased performance of the transistor devices. However, such advances do not come for free. Adverse effects in current implant designs are being witnessed, such as increasing power consumption, absence of design for reliability and highly application-specific nature. Operating under the assumption that implants will constitute an important means towards improved, personal healthcare and, in view of the aforementioned design phenomena, we believe that a new paradigm in implant design is required. This dissertation establishes the concept of Smart implantable Medical Systems (SiMS). SiMS is a systematic approach – a framework – for providing biomedical researchers and, hopefully, industry with a toolbox of ready-to-use, highly reliable implant sub-systems and models in order to construct optimal implants for various medical applications. The SiMS framework has to guarantee essential attributes, such as high dependability, modular design, ultra-low power consumption and miniature size. Having defined the SiMS framework, this dissertation is, then, concerned with exploring the optimal microarchitectural details of a crucial SiMS component: the SiMS processor. Contrary to the current state of the art, this processor aspires to be a new universal, low-power and low-cost processor and capable of efficiently serving a wide range of diverse implant applications.Computer Science and EngineeringElectrical Engineering, Mathematics and Computer Scienc
Exploring suitable Adder Designs for Biomedical Implants: A gracefully-degradable, fault-tolerant, and highly resource-constrained adder for SiMS
No full textModern applications demand extremely low power budgets in computer architectures for battery-operated devices. In the particular case of implantable devices —the main focus of this thesis— the system must have a long life span and batteries may not be possible or easy to recharge. In addition to power, chip area is also of major concern in this specific scenario. Since implantable devices are sometimes placed at locations inside the body where limited space is available, the implant must be as small as possible. The vast amount of volume of an implant is typically occupied by the battery and its electrodes, so the affordable chip area is very limited. Another reason why we want very small processor cores, is because this approach leaves more space for cache memory and it statistically reduces the chance of hardware failures. In this thesis we focus on the arithmetic unit (AU) of such a core, which is typically the adder/subtracter. The goal is to explore existing fault-tolerant and low-power AUs which are suitable for implementation in biomedical implants. A second objective is to study our own idea for a resource-constrained AU, based on graceful degradation: the so-called scalable arithmetic unit (ScAU). When an error occurs, the ScAU is able to proceed with the computational work, but no longer at the normal throughput: instead of single-cycle we downgrade to double-cycle operations. The design of our ScAU as well as several reference designs are all implemented in VHDL, synthesized and analyzed using Synopsys Design Compiler/PrimeTime and ModelSim. A major part of this thesis is dedicated to fault-tolerant design. An extensive study among common and less frequently employed error-detection schemes is performed. Finally, an error-detection scheme is chosen, applied to the ScAU, as well as to the reference designs for providing fair comparisons. A simple error-correction scheme is implemented as well. The fault-tolerant ScAU proves to have some very interesting advantages over the current state of the art. The fault-tolerant ScAU saves 17% of area, with a speedup of 12% for a 7.3% increase in power consumption, compared to the conventional technique with the lowest costs. Because of these savings, the power-delay-area product reduces by almost 21%. Under specific circumstances, our fault-tolerant ScAU is even capable of saving both area and power.Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Towards high-level synthesis of neural models on FPGAs
No full textRecent trends in studying the brain activity have attracted interest in the simulation of neurons to understand the brain functionality. However, these simulations are computationally intensive and time consuming, which limits this study. High-performance FPGA-based platforms are being utilized to accelerate these simulations. However, the transformation of sequential code to a data flow graph, the scheduling of operations for an efficient use of resources, the generation of hardware description code, the simulation and synthesis are tedious and time consuming tasks. Furthermore, the design space is huge and various scheduling algorithms need to be evaluated based upon variants of area-delay cost metrics to make decisions. An open source tool has been developed at TUDelft to automate this process, which considerably reduces the implementation time. This tool allows us to schedule, plot, explore the design space and generate VHDL code. We have utilized this tool in order to implement in hardware, a detailed neural network model of the inferior olive module in the brain. In order to support the model's mathematical requirements, we have extended the tool with three more operations and added the support for floating-point arithmetic. Based on various cost metrics, two Pareto points were chosen for synthesis. The neural network model was synthesized at the granularity level of 1, 2 and 4 neurons. Performance analysis of the synthesis results shows that, in the best case, we were able to achieve a speedup of 80% over real-time execution for 500 neurons. We have also showed that using smaller neuron cells results in higher speedup and better area utilization.Computer EngineeringMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Profiling symmetric encryption algorithms for implantable medical devices
No full textThe amount of Implantable Medical Devices (IMD) keeps booming in recent years. However, not many of them have encryption and decryption methods to protect their data communication. The purpose of this thesis work is to profile various popular symmetric encryption algorithms and select the best candidates as the benchmark for generic IMD. Moreover, this thesis gives suggestions for design digital CPU for generic IMD based on lab work simulation output. This thesis work will focus on profiling and analyzing several metrics: average power consumption, peak power consumption and energy consumption of all candidates because those metrics are the crucial constraint of IMD. Also the background information of all candidates will be introduced and all relevant metrics such as security level, encryption rates of all candidates will be discussed in this thesis work.Electrical Engineering, Mathematics and Computer Scienc
Heuristic Search for Defect Tolerant Multiprocessor Arrays
No full textIn this paper, new heuristic-search methods and algorithms are presented for enabling highly efficient and adaptive, defect-tolerant multiprocessor arrays. We consider systems where a homogeneous multiprocessor array lies on top of reconfigurable interconnects which allow the pipeline stages of the processors to be connected in all possible configurations. Considering the multiprocessor array partitioned in substitutable units at the granularity of pipeline stages, we employ a variety of heuristic-search methods and algorithms to isolate and replace defective units. The proposed heuristics are designed for off-line execution and aim at minimizing the performance overhead necessarily introduced to the array by the interconnects' latency. An empirical evaluation of the designed algorithms is then carried out, in order to assess the targeted problem and the efficacy of our approach. Our findings indicate this to be a NP-complete computational problem, however, our heuristic-search methods can achieve 100% accuracy in finding the optimal solution among 10^19 possible candidates within 2.5 seconds. Alternatively, they can provide near-optimal solutions at an accuracy which consistently exceeds 70% (compared to the optimal solution) in only 10^-4 seconds.Computer EngineeringComputer Science and EngineeringElectrical Engineering, Mathematics and Computer Scienc
Architecture-Level Fault-Tolerance Techniques for Biomedical Implants
No full textIn this thesis the design and implementation of a new fault-tolerant architecture is described. The design targets both soft and hard faults by implementing a combination of known fault-tolerance tech niques in an efficient way. The proposed architecture allows a trade-off to be made between performance and fault tolerance by means of instruction-level configurability. The design is evaluated in terms of fault coverage, area, average power consumption, total energy consumption and performance for various duplication policies and test-sequence schedules. It is shown that an area and power overhead of roughly 25% and 32%, respectively, are required to implement the techniques on the baseline processor. The main overheads of the architecture are performance (up to 106%) and energy consumption (up to 157%). It is observed that the average power consumption is often reduced when a higher degree of fault tolerance is set and therefore the energy consumption does not increase linearly with a higher execution time. It is shown that test sequences can effectively be scheduled during program stalls, and that nearly 100% of all soft faults are tolerated by using instruction duplication. The main advantages of using our techniques are the flexibility to make a trade-off between the overheads and the required degree of fault tolerance, the high portability of the used techniques and the small increase in area and power consumption.Computer EngineeringMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
An Adaptive Defect-Tolerant Multiprocessor Array Architecture
No full textRecent trends in transistor technology have dictated the constant reduction of device size. One negative effect stemming from the reduction in size and increased complexity is reduced reliability. This thesis is centered around the matter of fault recovery, in the subject of device fault-tolerance, and graceful system degradation in the presence of hard faults. Using a sparing strategy to re-use functional pipeline stages of faulty cores, we take advantage of the natural redundancy of multi-cores. This is done by the incorporation of a re-configurable network in which the cores of the system sit upon and has the ability to re-direct the data flow from the faulty pipeline stages of damaged cores to spare functional ones. The implementation requires the absence of global signals and thus pipeline stage operation needs to be decoupled. We also develop the bi-directional switch required for the network and implement a 4-core working example of our architecture as proof of concept and to evaluate the design. The 4-core design can guarantee correct functionality with 75% of system non-functional, in the best case scenario. The Defect-Tolerant pipeline has overhead of 1.92% in execution cycles and 14.4% in terms of operating frequency, for our custom made stress-marks. Such a system implemented with un-pipelined interconnect would lead to a pipeline with 50% lower frequency and x 2.1 longer overall execution time when the system has no faults. With our architecture and pipelined interconnect the frequency overhead is reduced by 34% and the overall execution time cost by 28% in the full 4-core system. The total execution time overhead, for our stress-marks, in the complete system ranges from x 1.5 to x 3.8 compared to the baseline, depending on the number of defects in the array. The area overhead is around 69% and power consumption, without incorporating any advanced power saving technique, is estimated between x 4 to x 5 times higher compared to the baseline.Computer EngineeringComputer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Automated Implant-Processor Design
No full textAs we move towards an aging population, it is likely that an increasing number of people will require an increasing diversity of implants, but at a lower cost to the society. Also, as computer technology progresses, smaller, more powerful, and less battery intensive implants can be designed. However, present implant design methodology is highly inefficient at meeting these goals as it suffers from non-reuse of existing knowledge by relying heavily on custom designs and ASICs. The SiMS project was started with the goal of creating pre-designed, pre-tested, and pre-certified toolbox of components for biomedical implants that can be assembled in a modular fashion for various application scenarios. One of the most important components in such a tool-box is the processor. Designing such a processor is a non-trivial task and previous work has concentrated on studying the effect of changing the processor input-parameters (such as caches), one parameter at a time. The present work represents a shift in this methodology, as we now allow co-variation in all possible input parameters in order to find optimal configurations in terms of the output objectives - power, performance, and area. Towards this end, we implement ImpEDE -- "Implantable-processor Evolutionary Design-space Explorer" -- a framework that performs multi-objective optimization of processor parameters, and hence gives as output a Pareto optimal set of processors. The framework consists of a cache simulator and a cycle-accurate processor simulator running benchmarks and workloads designed for medical implants, in order to simulate the optimization objectives. A popular, highly configurable, multi-objective genetic algorithm, NSGA-II, performs the actual optimization. Supporting scripts add modularity by acting as the interface between the genetic algorithm and the simulators, enabling easy replacement with new simulators. The whole framework is parallelized such that extra computation cycles of the idle laboratory CPUs can be utilized, thereby giving a considerable speedup without requiring any special hardware. We perform experiments on the non-dominated solution fronts evolved by the framework on a sub-set of benchmarks, in order to optimize parameters of the genetic algorithm, with an aim towards speeding up convergence. We also examine the effects of changing the workload size run by the benchmarks. A solution Pareto optimal front consisting of optimal processor configurations across all benchmarks is found. This front is used as a reference in order to characterize the benchmarks in the ImpBench suite. Finally, the objective space of the reference front is compared to existing implant designs, and a set of "generic processors" are chosen such that all the existing implant applications studied can be covered.Computer EngineeringComputer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Next-generation neuromodulator for epilepsy prevention
No full textClosed-loop neurostimulation systems have emerged as a prominent method for treating seizures. However, most of the proposed solutions do not consider the need for fast (real-time) seizure detection or their energy overheads, resulting in systems not suitable for wearable or implantable applications. This thesis describes the design and implementation of a novel closed-loop system that is capable of real-time seizure detection and suppression, while requiring minimal power and energy consumption. The proposed system utilizes a complex Morlet wavelet in combination with a thresholding mechanism to detect the presence of ictal-activity in ECoG signals. We evaluate our system in terms of detection performance (sensitivity, specificity and delay) considering various filter parameters, such as the filter order and various (static) detection thresholds. Additionally, we consider the system’s suitability for implantable applications by evaluating its computational overheads (execution time, energy consumption) when executed on the SiMS low-power processor. We show that decreasing the filter order results in less accurate detection (sensitivity, specificity), a faster detection (delay), and less overheads. In addition, we show that we may further improve the detection accuracy and delay with minimal overheads by considering an input-dependent (adaptive) threshold mechanism. Furthermore, we show that we can effectively trade-off detection accuracy and energy consumption: For example, shrinking filter order by 70% results in a decrease in detection accuracy of only 1%, while allowing us to obtain an improvement in delay by 190 ms (from 710 ms to 520 ms) and in energy consumption by 70% (from 5.04?J to 1.51?J). Compared to related work, we show that we can detect seizures significantly faster (492 ms, compared to 970 ms) with the same sensitivity (94%) and at a minimal decrease in specificity of 4.6% (93.60% compared to 98.2%). A prototype implementation of the closed-loop system has successfully been applied in in-vivo experiments, demonstrating its potential for epilepsy treatment.Computer EngineeringBioelectronicsElectrical Engineering, Mathematics and Computer Scienc
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