830 research outputs found
Overcoming steroid resistance in T cell acute lymphoblastic leukemia
No full textIn a Perspective, Pieter Van Vlierberghe and Steven Goossens discuss Meijerink and colleagues' findings on steroid resistance in pediatric T cell acute lymphoblastic leukemia
Nano particles play with electrons: Fundamental research into electron transport inside dye-sensitised solar cells
No full textWere stuck with a chicken-and-egg-problem: solar cells are expensive, so they dont get sold, which keeps the production volume low, so the price remains high.However, within a decade the price of electricity from a solar panel will be comparable to that of conventional mains power, says Dr. Albert Goossens, associate professor at the laboratory for Inorganic Chemistry at tu delft.He is currently investigating new methods and, in particular, new materials, that will render the production of electricity from solar energy more efficient. The special focus is on the Graetzel cell, a solar cell based on titanium dioxide (TiO2). Measurements of the speed of electrons led Goossens to the surprising conclusion that titanium dioxide nano particles behave like quantum dots
A biomechanical testing system to determine micromotion between hip implant and femur accounting for deformation of the hip implant: Assessment of the influence of rigid body assumptions on micromotions measurements
No full textAccurate pre-clinical evaluation of the initial stability of new cementless hip stems using in vitro micromotion measurements is an important step in the design process to assess the new stem's potential. Several measuring systems, linear variable displacement transducer-based and other, require assuming bone or implant to be rigid to obtain micromotion values or to calculate derived quantities such as relative implant tilting.sponsorship: This study was supported by the BVOT (Belgian Association of Orthopedics and Traumatology) (Micromotion Setup Project). Steven Leuridan was funded by a scholarship of IWT (Agency for Technology and Innovation, Flanders) (SB 81092). Quentin Goossens was supported by the KU Leuven Impulse Fund (ZKC8260-00-W01). (BVOT (Belgian Association of Orthopedics and Traumatology) (Micromotion Setup Project), IWT (Agency for Technology and Innovation, Flanders)|SB 81092, KU Leuven Impulse Fund|ZKC8260-00-W01)status: Publishe
New insights on accretion in supergiant fast X-ray transients from XMM-Newton and INTEGRAL observations of IGR J17544-2619
No full textXMM–Newton observations of the supergiant fast X-ray transient IGR J17544?2619 are reported and placed in the context of an analysis of archival INTEGRAL/IBIS data that provide a refined estimate of the orbital period at 4.9272?±?0.0004?d. A complete outburst history across the INTEGRAL mission is reported. Although the new XMM–Newton observations (each lasting ?15 ks) targeted the peak flux in the phase-folded hard X-ray light curve of IGR J17544?2619, no bright outbursts were observed, the source spending the majority of the exposure at intermediate luminosities of the order of several 1033?erg?s?1 (0.5–10 keV) and displaying only low level flickering activity. For the final portion of the exposure, the luminosity of IGR J17544?2619 dropped to ?4?×?1032?erg?s?1 (0.5–10 keV), comparable with the lowest luminosities ever detected from this source, despite the observations being taken near to periastron. We consider the possible orbital geometry of IGR J17544?2619 and the implications for the nature of the mass transfer and accretion mechanisms for both IGR J17544?2619 and the supergiant fast X-ray transients (SFXTs) population. We conclude that accretion under the ‘quasi-spherical accretion’ model provides a good description of the behaviour of IGR J17544?2619 and suggests an additional mechanism for generating outbursts based upon the mass accumulation rate in the hot shell (atmosphere) that forms around the neutron star under the quasi-spherical formulation. Hence, we hope to aid in explaining the varied outburst behaviours observed across the SFXT population with a consistent underlying physical model
A nondestructive method to verify the glenosphere-baseplate assembly in reverse shoulder arthroplasty
No full textGlenoid dissociation is a rare postoperative complication in reverse shoulder arthroplasty that has severe consequences for the patient and requires revision in most cases. A mechanically compromised Morse taper is hypothesized to be the main cause of this complication, with bony impingements and soft tissue interpositioning being cited as the most important problems. Intraoperative assessment of the taper assembly is challenging. Current methods require applying considerable torque to the glenosphere or relying on radiographs.sponsorship: This study was supported by the BVOT (Belgian Association of Orthopedics and Traumatology). Steven Leuridan was funded by a scholarship from IWT (Agency for Technology and Innovation, Flanders). Quentin Goossens was supported by the KU Leuven Impulse Fund. (BVOT (Belgian Association of Orthopedics and Traumatology), IWT (Agency for Technology and Innovation, Flanders), KU Leuven Impulse Fund)status: Publishe
Multithreading for Embedded Reconfigurable Multicore Systems
No full textIn this dissertation, we address the problem of performance efficient multithreading execution on heterogeneous multicore embedded systems. By heterogeneous multicore embedded systems we refer to those, which have real-time requirements and consist of processor tiles with General Purpose Processor (GPP), local memory, and one or more coprocessors running on reconfigurable logic ((e)FPGA). We improve system performance by combining two common methods. The first method is to exploit the available application parallelism by means of multithreading program execution. The second method is to provide hardware acceleration for the most computationally intensive kernels. More specifically our scientific approach is as follows: we categorize the existing program execution models from the processor-coprocessor synchronization prospective and we introduce new parallel execution models. Then, we provide a high-level architectural abstraction of those execution models and programming paradigm that describes and utilizes them. Furthermore, we propose a microarchitectural support for the identified execution models. The functionality of the microarchitectural extensions is encapsulated in a new reconfigurable coprocessor, called Thread Interrupt State Controller (TISC). To improve the overall system performance, we employ the newly proposed program execution models to transfer highly time-variable and time-consuming Real-Time Operating System (RTOS) and application kernels from software, i.e., executed on the GPPs, to hardware, i.e., executed on the reconfigurable coprocessors. We refer to this reconfigurable coprocessor as Hardware Task Status Manager (HWTSM). Due to the properties of the newly introduced execution models such as parallel execution and constant response time, we preserve the predictability and composability at application level. Last but not least, we introduce a framework for distribution of slack information (idle processor time) among processor tiles. In the proposed framework we employ one of the newly introduced parallel processor-coprocessor execution models. We refer to the new reconfigurable coprocessor as RS. We use the extra slack information obtained through our framework for Dynamic Voltage Frequency Scaling that reduces the overall energy consumption. Based on the available experimental results with synthetic and real applications, we improve the system speedup up to 19.6 times with the help of the Thread Interrupt State Controller. Furthermore, we reduce RTOS cost with the help of the Hardware Task Status Manager, which results in additional application acceleration up to 13.3%. Last but not least, we improve the system energy consumption up to 56.7% over current state of the art with the help of inter-tile remote slack information distribution framework. Overall, with the help of our contributions, the system performance is improved, the predictability and composability are preserved, all with reduced energy consumption.Software and Computer TechnologyElectrical Engineering, Mathematics and Computer Scienc
Better than Worst-Case Design for Streaming Applications under Process Variation
No full textComputer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Reconfigurable network processing platforms
No full textThis dissertation presents our investigation on how to efficiently exploit reconfigurable hardware to design flexible, high performance, and power efficient network devices capable to adapt to varying processing requirements of network applications and traffic. The proposed reconfigurable network processing platform targets mainly access, edge, and enterprise devices. These devices have to sustain less bandwidth compared to those utilized in core networks. However the processing requirements on a per packet basis are much higher in these devices (e.g., payload processing). Furthermore, devices in these networks have to be flexible in order to support emerging network applications. A promising technology for the implementation of these devices is the Field-Programmable Gate Arrays (FPGAs). FPGAs are typical devices that combine flexibility (through the reconfiguration) and performance (through the inherent hardware nature that can exploit parallelism), therefore they can efficiently address the requirements of the edge and access network devices. A reconfigurable network processing platform is presented that includes reconfigurable hardware accelerators, a reconfigurable queue scheduler, and a configurable transactional memory controller. Furthermore, the performance and the constraints of the platform are formulated as an integer optimization problem and an integrated design flow is presented for the platform. Both static and dynamic reconfiguration is explored in this dissertation. Static reconfiguration is utilized to address the different processing requirements of network applications, while dynamic reconfiguration is utilized to adapt to network traffic fluctuations. Two representative devices were implemented and evaluated in the proposed platform; a multi-service edge router and a content-based (web) switch. In the former device, dynamic reconfiguration is utilized to deal with network traffic fluctuations. The device monitors the traffic and adapts to the network traffic fluctuations taking into account the reconfiguration overhead. In the latter device, a reconfigurable architecture for a content-based switch is utilized and compared to a mainstream network processor in terms of performance and power. The device accommodates several co-processors that can be interchanged to perform specific type of switching (e.g., URL-based or cookie-based switching). Moreover, the exploitation of reconfigurable logic is investigated for queue scheduling in network devices. A reconfigurable queue scheduler is presented that adapts to the network traffic requirements (number of active queues) and can be used both in edge routers and web switches. Finally, configurable transactional memories are proposed which can be used to efficiently deploy multi-processing platforms for network processing applications. The proposed configurable transactional memory controller can be configured based on the application and device features (e.g., number of processors), can offer an easier programming framework for multi-processor reconfigurable platforms, and provides increased performance compared to traditional locking schemes. The results of the research presented in this dissertation show that the FPGAs can be an efficient alternative to network processors and can be used not only for lower network layers, but also as a complete platform for emerging network processing applications.Electrical Engineering, Mathematics and Computer Scienc
A Cache-Based Hardware Accelerator for Memory Data Movements
No full textThis dissertation presents a hardware accelerator that is able to accelerate large (including non-parallel) memory data movements, in particular memory copies, performed traditionally by the processors. As todays processors are tied with or have integrated caches with varying sizes (from several kilobytes in hand-held devices to many megabytes in desktop devices or large servers), it is only logical to assume that data to-be-copied by a memory copy is already present within the cache. This is especially true when considering that such data often must be processed first. This means that the presence of the caches can be utilized to significantly reduce the latencies associated with memory copies, when a smarter way to perform the memory copy operation is used. Therefore, the proposed accelerator for memory copies takes advantage of the presence of these caches and introduces a redirection mechanism that links the original data (in the cache) to the copied addresses (in a newly added indexing table). The proposed solutions avoid cache pollution and duplication of data, and efficiently schedule the access to the main memory, thus effectively reducing the latency associated with memory copies. Moreover, the proposed accelerator supports copies of cache line and word granularity, can be connected to a direct-mapped or a set-associative cache, and can efficiently reduce the memory copy bottleneck in single core processors and in multi-core processors that execute a message passing communication model. The proposed solutions have been implemented in a FPGA as a proof of concept and incorporated in a simulator running several benchmarks to determine the performance gains of the proposal. In particular, for the receiver side of the TCP/IP stack, the proposed solutions can reach speedups from 2.96 to 4.61 times and reduce the number of instructions executed by 26% to 44%.Electrical Engineering, Mathematics and Computer Scienc
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